| Design of a low power, high speed double tail comparator S Aakash, A Anisha, GJ Das, T Abhiram, JP Anita 2017 International Conference on Circuit, Power and Computing Technologies …, 2017 | 17 | 2017 |
| A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults N Mohan, JP Anita International Journal of Mathematical Modelling and Numerical Optimisation 7 …, 2016 | 13 | 2016 |
| Efficient don't-care filling method to achieve reduction in test power V Sinduja, S Raghav, JP Anita 2015 International Conference on Advances in Computing, Communications and …, 2015 | 13 | 2015 |
| Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits JP Anita, PT Vanathi 2014 International Conference on Electronics and Communication Systems …, 2014 | 12 | 2014 |
| Modified carry select adder for power and area reduction T Abhiram, T Ashwin, B Sivaprasad, S Aakash, JP Anita 2017 International conference on circuit, power and computing technologies …, 2017 | 8 | 2017 |
| Multiple fault diagnosis and test power reduction using genetic algorithms JP Anita, PT Vanathi International Conference on Eco-friendly Computing and Communication Systems …, 2012 | 8 | 2012 |
| Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams JP Anita, P Sudheesh International Journal of High Performance Systems Architecture 6 (1), 51-60, 2016 | 7 | 2016 |
| Design of multistage counters using linear feedback shift register NB Nair, JP Anita Inventive Communication and Computational Technologies: Proceedings of …, 2022 | 6 | 2022 |
| Implementation of hybrid LBIST mechanism in digital circuits for test pattern generation and test time reduction PA Kumar, JP Anita 2020 5th International Conference on Communication and Electronics Systems …, 2020 | 6 | 2020 |
| Nonlinear state estimation of wind turbine P Sudev, JP Anita, P Sudheesh 2017 International Conference on Advances in Computing, Communications and …, 2017 | 6 | 2017 |
| Multistage test data compression technique for VLSI circuits A Asokan, JP Anita 2016 International Conference on Advanced Communication Control and …, 2016 | 6 | 2016 |
| Design of a high-speed binary counter using a stacking circuit C Devika, JP Anita Inventive Communication and Computational Technologies: Proceedings of …, 2022 | 5 | 2022 |
| Compact test and diagnosis pattern generation for multiple fault pairs in single run N Mohan, JP Anita Journal of Engineering Science and Technology 15 (6), 3820-3835, 2020 | 5 | 2020 |
| Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits CN Kumar, A Madhumitha, NS Preetam, PV Gupta, JP Anita 2019 3rd International conference on trends in electronics and Informatics …, 2019 | 5 | 2019 |
| A compaction based MT filling technique for low-power test set generation GV Madhavi, JP Anita 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 5 | 2016 |
| Application Specific Testing for VLSI Benchmark Circuits K Abinandhan, K Gurucharan, M Purnima, SS Vandana, JP Anita 2022 7th International Conference on Communication and Electronics Systems …, 2022 | 4 | 2022 |
| Structured DFT based analysis of standard benchmark circuits H Harshita Shravani, JP Anita Emerging Trends in Electrical, Communications, and Information Technologies …, 2020 | 4 | 2020 |
| Online state and parameter estimation of ultracapacitor using marginalized Kalman filter S Madhumitha, P Sudheesh, JP Anita 2019 International Conference on Intelligent Computing and Control Systems …, 2019 | 4 | 2019 |
| Burrows wheeler transform based test vector compression for digital circuits A Asokan, JP Anita Indian Journal of Science and Technology, 2016 | 4 | 2016 |
| Pattern generation and test compression using presto generator A Roy, JP Anita Security in Computing and Communications: 5th International Symposium, SSCC …, 2017 | 3 | 2017 |
