| FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL AK Panda, P Rajput, B Shukla 2012 International Conference on Communication Systems and Network …, 2012 | 99 | 2012 |
| Modified dual-CLCG method and its VLSI architecture for pseudorandom bit generation AK Panda, KC Ray IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 989-1002, 2019 | 39 | 2019 |
| A coupled variable input LCG method and its VLSI architecture for pseudorandom bit generation AK Panda, KC Ray IEEE Transactions on Instrumentation and Measurement 69 (4), 1011-1019, 2020 | 33 | 2020 |
| FPGA implementation of 16 bit BBS and LFSR PN sequence generator: A comparative study K Sewak, P Rajput, AK Panda 2012 IEEE Students' Conference on Electrical, Electronics and Computer …, 2012 | 32 | 2012 |
| High-speed area-efficient VLSI architecture of three-operand binary adder AK Panda, R Palisetty, KC Ray IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3944-3953, 2020 | 25 | 2020 |
| FPGA implementation of encoder for (15, k) binary BCH code using VHDL and performance comparison for multiple error correction control AK Panda, S Sarik, A Awasthi 2012 International Conference on Communication Systems and Network …, 2012 | 23 | 2012 |
| FPGA Prototype of Low Latency BBS PRNG AK Panda, KC Ray 2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015 | 18 | 2015 |
| Design and FPGA prototype of 1024-bit Blum-Blum-Shub PRBG architecture AK Panda, KC Ray 2018 IEEE International Conference on Information Communication and Signal …, 2018 | 14 | 2018 |
| Area-efficient parallel-prefix binary comparator AK Panda, R Palisetty, KC Ray 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 6 | 2019 |
| ASIC Implementation of Low PAPR Multi-Device Variable Rate Architecture for IEEE 802.11 ah R Palisetty, AK Panda, KC Ray IEEE Transactions on Instrumentation and Measurement 70, 1-10, 2021 | 1 | 2021 |
| Design and Implementation of (63, 45) Binary BCH code Encoder on Spartan 3 FPGA for Noisy Communication Channel AK Panda, N Tiwari | 1 | 2012 |
| Dual Arbiter PUF with Shift Register Based TRNG on Basys-3 FPGA Board and its Performance Analysis on Uniqueness, Reliability and Randomness LD Singh, P Meher, AK Panda International Journal of Intelligent Systems and Applications in Engineering …, 2024 | | 2024 |
| A Smartphone Enabled Deep Learning Approach for Myocardial Infarction Detection Using ECG Traces for IoT-Based Healthcare Applications VS Parupudi, AK Panda, RK Tripathy IEEE Sensors Letters, 2023 | | 2023 |
| Design and implementation of an efficient pseudorandom bit generation method and its VLSI architecture AK Panda Patna, 2020 | | 2020 |
| Secure OFDM based on Coupled Linear Congruential Generator and its FPGA Prototype R Palisetty, AK Panda, KC Ray 2018 IEEE International Conference on Information Communication and Signal …, 2018 | | 2018 |
| iSES 2019 T Pal, S DasBit, P Khatua, KC Ray, AK Panda, R Palisetty, SA Islam, ... | | |
Rakesh PalisettyPostdoc Research Associate, University of LuxembourgVerified email at uni.lu
