Prof. Dipankar Pal
Prof. Dipankar Pal
Professor, Dept. of EEE and E&I, BITS-Pilani, Goa
Verified email at goa.bits-pilani.ac.in
Title
Cited by
Cited by
Year
Current conveyor-based square/triangular waveform generators with improved linearity
D Pal, A Srinivasulu, BB Pal, A Demosthenous, BN Das
IEEE Transactions on Instrumentation and Measurement 58 (7), 2174-2180, 2008
1102008
Very low-noise ENG amplifier system using CMOS technology
R Rieger, M Schuettler, D Pal, C Clarke, P Langlois, J Taylor, ...
IEEE Transactions on Neural Systems and Rehabilitation Engineering 14 (4†…, 2006
702006
An energy efficient multilayer MAC protocol (ML MAC) for wireless sensor networks
MK Jha, AK Pandey, D Pal, A Mohan
Int. Jl. of Electronics & Communication 65, 209-216, 2011
63*2011
A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier
C Sawigun, A Demosthenous, D Pal
2007 18th European Conference on Circuit Theory and Design, 751-754, 2007
322007
Thermal model of MOSFET with SELBOX structure
MR Narayanan, H Al-Nashash, D Pal, M Chandra
Journal of Computational Electronics 12 (4), 803-811, 2013
242013
Low‐power 6‐GHz wave‐pipelined 8b ◊ 8b multiplier
A Saha, D Pal, M Chandra
IET Circuits, Devices & Systems 7 (3), 124-140, 2013
192013
Novel current-mode waveform generator with independent frequency and amplitude control
D Pal, A Srinivasulu, M Goswami
2009 IEEE International Symposium on Circuits and Systems, 2946-2949, 2009
192009
Novel CMOS Multi-bit Counter for Speed- Power Optimization in Multiplier Design
AGNDP Aloke Saha, Rahul Pal
Int. J. Electron. Commun. (AE‹) 95, 189–198, 2018
18*2018
A low-power CMOS analog voltage buffer using compact adaptive biasing
C Sawigun, J Mahattanakul, A Demosthenous, D Pal
2007 18th European Conference on Circuit Theory and Design, 1-4, 2007
182007
Benchmarking of DPL-based 8b ◊ 8b novel wave-pipelined multiplier
DPMC Aloke Saha
International Journal of Electronics Letters 5 (1), 115-128, 2017
172017
Benchmarking of DPL-based 8b◊ 8b novel wave-pipelined multiplier
A Saha, D Pal, M Chandra
International Journal of Electronics Letters 5 (1), 115-128, 2017
172017
Combined economic and emission dispatch by ANN with backprop algorithm using variant learning rate & momentum coefficient
B Kar, KK Mandal, D Pal, N Chakraborty
2005 International Power Engineering Conference, 1-235, 2005
142005
Novel high speed MCML 8-bit by 8-bit multiplier
A Saha, D Pal, M Chandra, MK Goswami
2011 International Conference on Devices and Communications (ICDeCom), 1-5, 2011
132011
DPL-based novel binary-to-ternary converter on CMOS technology
ASD Pal
Int. J. Electron. Commun. (AE‹), 92, 69-73, 2018
112018
Novel, low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation
ASDP M. Sarada
International Journal of Electronics Letters 6 (3), 272-287, 2018
112018
Malnutrition scenario among school children in Eastern-India–an epidemiological study
D Pal, S Kanungo, B Bal, K Bhowmik, T Mahapatra, K Sarkar
Epidemiology (Sunnyvale) 6 (228), 2161-1165.1000228, 2016
112016
Analysis of kink reduction in SOI MOSFET using selective back oxide structure
M Narayanan, H Al-Nashash, B Mazhari, D Pal, M Chandra
Active and Passive Electronic Components 2012, 2012
112012
A wide-input linear range sub-threshold transconductor for sub-Hz filtering
C Sawigun, D Pal, A Demosthenous
Proceedings of 2010 IEEE International Symposium on Circuits and Systems†…, 2010
112010
Studies and minimization of kink effect in SOI MOSFET devices with SELBOX structure
MR Narayanan, H Al-Nashash, B Mazhari, D Pal
2008 International Conference on Microelectronics, 232-235, 2008
102008
Reactive power pricing in a deregulated electricity industry
KK Mandal, B Kar, D Pal, M Basu, N Chakraborty
2005 International Power Engineering Conference, 853-858, 2005
102005
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Articles 1–20