Digitally intensive sub-sampling mixer-first direct down-conversion receiver architecture R Rena, R Kammari, VSR Pasupureddi 2022 IEEE 65th International Midwest Symposium on Circuits and Systems …, 2022 | 3 | 2022 |
Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2 V, 65nm CMOS R Kammari, VSR Pasupureddi International Journal of Circuit Theory and Applications 48 (2), 198-213, 2020 | 3 | 2020 |
0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, + 10-dBm IB-IIP3 in 65-nm CMOS RV Rena, R Kammari, V Shankar P. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 2 | 2023 |
Modeling and Design of A Compact Low Power Folded Cascode OpAmp With High EMI Immunity R Kammari, J Gundla, S Boyapati, VSR Pasupureddi IEEE Transactions on Electromagnetic Compatibility, 2021 | 2 | 2021 |
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS R Kammari, VSR Pasupureddi International Symposium on VLSI Design and Test, 202-214, 2019 | 1 | 2019 |
A 0.4–1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End RV Rena, R Kammari, VS Pasupureddi IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | | 2023 |
A 1–6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS R Kammari, SR Tuckely, VS Pasupureddi 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 16-20, 2023 | | 2023 |
1Affiliation not available 2Indian Institute of Technology Bhubaneswar RV Rena, R Kammari, VS Pasupureddi | | 2023 |
An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects PK Govindaswamy, R Kammari, VSR Pasupureddi International Journal of Circuit Theory and Applications 51 (8), 3637-3651, 2023 | | 2023 |
APCCAS 2023 S Kumar, N Krishnapura, R Kammari | | |
Best Paper Awards S Kusumanchi, S Theertham, A Thakkar, N Krishnapura, R Kammari, ... | | |