| REVAMP: A systematic framework for heterogeneous CGRA realization TK Bandara, D Wijerathne, T Mitra, LS Peh Proceedings of the 27th ACM international conference on architectural …, 2022 | 61 | 2022 |
| Himap: Fast and scalable high-quality mapping on cgra via hierarchical abstraction D Wijerathne, Z Li, A Pathania, T Mitra, L Thiele IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 41 | 2021 |
| Chordmap: Automated mapping of streaming applications onto cgra Z Li, D Wijerathne, X Chen, A Pathania, T Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 41 | 2021 |
| Cascade: High throughput data streaming via decoupled access-execute cgra D Wijerathne, Z Li, M Karunarathne, A Pathania, T Mitra ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-26, 2019 | 40 | 2019 |
| 4D-CGRA: Introducing branch dimension to spatio-temporal application mapping on CGRAs M Karunaratne, D Wijerathne, T Mitra, LS Peh 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 35 | 2019 |
| Lisa: Graph neural network based portable mapping on spatial accelerators Z Li, D Wu, D Wijerathne, T Mitra 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 31 | 2022 |
| Morpher: An open-source integrated compilation and simulation framework for cgra D Wijerathne, Z Li, M Karunaratne, LS Peh, T Mitra Fifth Workshop on Open-Source EDA Technology (WOSET), 2022 | 23 | 2022 |
| PANORAMA: Divide-and-conquer approach for mapping complex loop kernels on CGRA D Wijerathne, Z Li, TK Bandara, T Mitra Proceedings of the 59th ACM/IEEE Design Automation Conference, 127-132, 2022 | 20 | 2022 |
| Coarse-Grained Reconfigurable Array (CGRA) Z Li, D Wijerathne, T Mitra Handbook of Computer Architecture, 1-41, 2022 | 8 | 2022 |
| Power-performance characterization of tinyml systems Y Zhang, D Wijerathne, Z Li, T Mitra 2022 IEEE 40th International Conference on Computer Design (ICCD), 644-651, 2022 | 8 | 2022 |
| Runtime rule-reconfigurable high throughput NIPS on FPGA PMK Tharaka, DMD Wijerathne, N Perera, D Vishwajith, A Pasqual 2017 International Conference on Field Programmable Technology (ICFPT), 251-254, 2017 | 8 | 2017 |
| FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow TK Bandara, D Wu, R Juneja, D Wijerathne, T Mitra, LS Peh 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| Accelerating Edge AI with Morpher: An Integrated Design, Compilation and Simulation Framework for CGRAs D Wijerathne, Z Li, T Mitra arXiv preprint arXiv:2309.06127, 2023 | 1 | 2023 |
| ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML P Dangi, Z Bai, R Juneja, D Wijerathne, T Mitra Proceedings of the 2024 International Conference on Parallel Architectures …, 2024 | | 2024 |
| PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications VP Nambiar, YS Chong, TK Bandara, D Wijerathne, Z Li, R Juneja, ... 2024 IEEE Hot Chips 36 Symposium (HCS), 1-1, 2024 | | 2024 |
| A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications VP Nambiar, YS Chong, TK Bandara, D Wijerathne, Z Li, R Juneja, ... 2024 21st International SoC Design Conference (ISOCC), 89-90, 2024 | | 2024 |
