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Dinesh Padole
Dinesh Padole
Professor, G.H.Raisoni College of Engineering, RTMNU Nagpur
Verified email at raisoni.net
Title
Cited by
Cited by
Year
A design approach to AMBA (Advanced Microcontroller Bus Architecture) bus architecture with dynamic lottery arbiter
K Warathe, D Padole, P Bajaj
2009 Annual IEEE India Conference, 1-4, 2009
152009
Dynamic lottery bus arbiter for shared bus system on chip: a design approach with VHDL
N Doifode, D Padole, P Bajaj
2008 First International Conference on Emerging Trends in Engineering and …, 2008
132008
Performance Evaluation of AES using Hardware and Software Codesign
VV Deotare, D Padole, AS Wakode
International Journal on Recent and Innovation Trends in Computing and …, 2014
102014
Design and performance analysis of efficient bus arbitration schemes for on-chip shared bus multi-processor soc
N Doifode, D Padole, PR Bajaj
Journal of Computer Science and Network Security 8, 250-255, 2008
102008
Arbitration schemes for multiprocessor shared bus
P Bajaj, D Padole
New Trends and Developments in Automotive System Engineering, 395-410, 2011
92011
Design of basic logic gates using carbon nano tube field effect transistor and calculation of figure of merit
P Yeole, DV Padole
2015 7th International Conference on Emerging Trends in Engineering …, 2015
72015
Performance analysis of CNFET based interconnect drivers for sub-threshold circuits
SS Chopade, SD Pable, DV Padole
International Journal of Computer Applications 60 (4), 2012
72012
Fuzzy arbiter based multi core system-on-chip integrated controller for automotive systems: A design approach
D Padole, P Bajaj
2008 Canadian Conference on Electrical and Computer Engineering, 001937-001940, 2008
72008
et. all,”
D Padole, PR Bajaj
Dynamic Lottery Bus Arbiter for Shared Bus-System on-chip: A Design Approach …, 2008
72008
Design of DG-CNFET for reduction of short channel effect over DG MOSFET at 20nm
SS Chopade, S Mane, D Padole
2013 IEEE International Conference of IEEE Region 10 (TENCON 2013), 1-5, 2013
62013
Configuration memory based dynamic coarse grained reconfigurable multicore architecture
D Padole, R Hiware
2013 IEEE International Conference of IEEE Region 10 (TENCON 2013), 1-5, 2013
52013
Efficient Implementation of Selective Image Encryption Technique on Multi-core Reconfigurable System
RK Hiware, DV Padole
International Journal of Applied Engineering Research 13 (8), 5715-5721, 2018
42018
The Design and Implementation of Handheld Multipurpose Scope Using Bluetooth IOIO Board
MKB Umare, DDV Padole
International Journal of Advanced Research in Computer Engineering …, 2015
42015
Stability analysis of 6T SRAM cell for nano scale FD-SOI technology
SS Chopade, DV Padole
2014 Annual IEEE India Conference (INDICON), 1-6, 2014
42014
Design of Double Gate MOSFET and FDSOI using high k material for nano scaled Circuits
SS Chopade, DV Padole
TENCON 2014-2014 IEEE Region 10 Conference, 1-5, 2014
42014
Brain machine interface system for person with quadriplegia disease
S Taksande, DV Padole
J. Comput. Appl. Technol. Res 3, 339-344, 2014
42014
Design of Cache Controller for Multi-core Systems using Multilevel Scheduling Method
VS Bhure, D Padole
2012 Fifth International Conference on Emerging Trends in Engineering and …, 2012
42012
Fuzzy Logic Arbiter for Shared Bus Multiprocessor System: A Design Approach
D Padole, P Bajaj
2008 First International Conference on Emerging Trends in Engineering and …, 2008
42008
Preeti Bajaj,“
D Padole, D Deepsheekha
Fuzzy Logic Arbiter for Shared Bus Multiprocessor System.: A Design Approach …, 2008
42008
Development of Feature based Hybrid Method for Brain Signature Identification
S Dongare, D Padole
2019 9th International Conference on Emerging Trends in Engineering and …, 2019
32019
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