Carl Seger
Carl Seger
Verified email at chalmers.se
TitleCited byYear
Asynchronous circuits
JA Brzozowski, CJH Seger
Springer Science & Business Media, 2012
3372012
Formal verification by symbolic evaluation of partially-ordered trajectories
CJH Seger, RE Bryant
Formal Methods in System Design 6 (2), 147-189, 1995
3351995
Formally verifying IEEE compliance of floating-point hardware
J O’Leary, X Zhao, R Gerth, CJH Seger
Intel Technology Journal 3 (1), 1-14, 1999
1521999
Formal hardware verification by symbolic ternary trajectory evaluation
RE Bryant, DL Beatty, CJH Seger
figshare, 1975
1431975
An industrially effective environment for formal hardware verification
CJH Seger, RB Jones, JW O'Leary, T Melham, MD Aagaard, C Barrett, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
1072005
Vos: A Formal Hardware Verification System User's Guide
CJH Seger
University of British Columbia. Department of Computer Science, 1993
1001993
Formal verification of digital circuits using symbolic ternary system models
RE Bryant, CJH Seger
International Conference on Computer Aided Verification, 33-43, 1990
921990
Formal verification using parametric representations of Boolean constraints
MD Aagaard, RB Jones, CJH Seger
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 402-407, 1999
891999
Linking BDD-based symbolic evaluation to interactive theorem-proving
JJ Joyce, CH Seger
30th ACM/IEEE Design Automation Conference, 469-474, 1993
881993
Introduction to generalized symbolic trajectory evaluation
J Yang, CJH Seger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (3), 345-353, 2003
842003
Combining theorem proving and trajectory evaluation in an industrial environment
MD Aagaard, RB Jones, CJH Seger
Proceedings of the 35th annual Design Automation Conference, 538-541, 1998
841998
The formal verification of a pipelined double-precision IEEE floating-point multiplier
MD Aagaard, CJH Seger
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
831995
Symbolic trajectory evaluation
S Hazelhurst, CJH Seger
Formal Hardware Verification, 3-78, 1997
731997
A simple theorem prover based on symbolic trajectory evaluation and BDD's
S Hazelhurst, CJH Seger
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
711995
Lifted-fl: A pragmatic implementation of combined model checking and theorem proving
MD Aagaard, RB Jones, CJH Seger
International Conference on Theorem Proving in Higher Order Logics, 323-340, 1999
691999
Practical formal verification in microprocessor design
RB Jones, JW O'Leary, CJH Seger, MD Aagaard, TF Melham
IEEE design & test of computers 18 (4), 16-25, 2001
592001
Generalized symbolic trajectory evaluation—abstraction in action
J Yang, CJH Seger
International Conference on Formal Methods in Computer-Aided Design, 70-87, 2002
582002
A Methodology for Formal Hardware Verification, with Application to Microprocessors.
DL Beatty, RE Bryant, EM Clarke Jr, AL Fisher, CJH Seger
CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE, 1993
561993
The HOL-Voss system: Model-checking inside a general-purpose theorem-prover
J Joyce, C Seger
HOL Users' Group Workshop, 185-198, 1993
561993
Advances in asynchronous circuit theory, Part II: Bounded inertial delay models, MOS circuits, design techniques
JA Brzozowski, CJH Seger
Bulletin of the European Association for Theoretical Computer Science 43 …, 1991
501991
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