| Embedded deterministic test J Rajski, J Tyszer, M Kassab, N Mukherjee IEEE transactions on computer-aided design of integrated circuits and …, 2004 | 641 | 2004 |
| Embedded deterministic test for low cost manufacturing test J Rajski, J Tyszer, M Kassab, N Mukherjee, R Thompson, KH Tsai, ... Proceedings. International Test Conference, 301-310, 2002 | 482 | 2002 |
| Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Y Huang, SM Reddy, WT Cheng, P Reuter, N Mukherjee, CC Tsai, ... Proceedings. International Test Conference, 74-82, 2002 | 213 | 2002 |
| Test pattern compression for an integrated circuit test environment J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,327,687, 2001 | 205* | 2001 |
| Method and apparatus for selectively compacting test responses J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,557,129, 2003 | 189* | 2003 |
| Resource allocation and test scheduling for concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... Proceedings 10th Asian Test Symposium, 265-270, 2001 | 185 | 2001 |
| Decompressor/PRPG for applying pseudo-random and deterministic test patterns J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,684,358, 2004 | 180* | 2004 |
| Reduced-pin-count-testing architectures for applying test patterns N Mukherjee, J Jahangiri, R Press, WT Cheng US Patent 7,487,419, 2009 | 80 | 2009 |
| Continuous application and decompression of test patterns to a circuit-under-test J Rajski, M Kassab, N Mukherjee, J Tyszer US Patent 7,478,296, 2009 | 80 | 2009 |
| Single-cell profiling of Ebola virus disease in vivo reveals viral and host dynamics D Kotliar, AE Lin, J Logue, TK Hughes, NM Khoury, SS Raju, ... Cell 183 (5), 1383-1401. e19, 2020 | 78 | 2020 |
| Analysis and comparative study of different converter modes in modular second-life hybrid battery energy storage systems N Mukherjee, D Strickland IEEE Journal of Emerging and Selected Topics in Power Electronics 4 (2), 547-563, 2015 | 76 | 2015 |
| Full-speed field-programmable memory BIST architecture X Du, N Mukherjee, WT Cheng, SM Reddy IEEE International Conference on Test, 2005., 9 pp.-1173, 2005 | 75 | 2005 |
| Method for synthesizing linear finite state machines J Rajski, J Tyszer, M Kassab, N Mukherjee US Patent 6,353,842, 2002 | 74* | 2002 |
| Embedded deterministic test for low-cost manufacturing J Rajski, M Kassab, N Mukherjee, N Tamarapalli, J Tyszer, J Qian IEEE Design & Test of Computers 20 (5), 58-66, 2003 | 72 | 2003 |
| On-chip comparison and response collection tools and techniques N Mukherjee, J Rajski, J Tyszer US Patent 7,913,137, 2011 | 63 | 2011 |
| Method and apparatus for selectively compacting test responses J Rajski, M Kassab, N Mukherjee, J Tyszer US Patent 7,500,163, 2009 | 63 | 2009 |
| X-press compactor for 1000x reduction of test data J Rajski, J Tyszer, G Mrugalski, N Mukherjee, M Kassab 2006 IEEE International Test Conference, 1-10, 2006 | 63 | 2006 |
| Bist architecture for detecting path-delay faults in a sequential circuit S Bhawmik, TJ Chakraborty, N Mukherjee US Patent 6,148,425, 2000 | 63 | 2000 |
| At-speed built-in self-repair analyzer for embedded word-oriented memories X Du, SM Reddy, WT Cheng, J Rayhawk, N Mukherjee 17th International Conference on VLSI Design. Proceedings., 895-900, 2004 | 62 | 2004 |
| Deterministic clustering of incompatible test cubes for higher power-aware EDT compression D Czysz, G Mrugalski, N Mukherjee, J Rajski, P Szczerbicki, J Tyszer IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 58 | 2011 |
