Nanomagnet logic: progress toward system-level integration MT Niemier, GH Bernstein, G Csaba, A Dingler, XS Hu, S Kurtz, S Liu, ... Journal of Physics: Condensed Matter 23 (49), 493202, 2011 | 231 | 2011 |
A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers TW Andre, JJ Nahas, CK Subramanian, BJ Garni, HS Lin, A Omair, ... IEEE journal of solid-state circuits 40 (1), 301-309, 2005 | 198 | 2005 |
Sense amplifier bias circuit for a memory having at least two distinct resistance states JJ Nahas, TW Andre, BJ Garni US Patent 6,700,814, 2004 | 195 | 2004 |
A 0.18/spl mu/m 4 Mbit toggling MRAM M Durlam, D Addie, J Akerman, B Butcher, P Brown, J Chan, M DeHerrera, ... 2004 International Conference on Integrated Circuit Design and Technology …, 2004 | 159 | 2004 |
Two-dimensional heterojunction interlayer tunneling field effect transistors (thin-TFETs) MO Li, D Esseni, JJ Nahas, D Jena, HG Xing IEEE Journal of the Electron Devices Society 3 (3), 200-207, 2015 | 154 | 2015 |
Analog circuit design using tunnel-FETs B Sedighi, XS Hu, H Liu, JJ Nahas, M Niemier IEEE transactions on circuits and systems I: regular papers 62 (1), 39-48, 2014 | 130 | 2014 |
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics CK Subramanian, JJ Nahas US Patent 6,944,052, 2005 | 103 | 2005 |
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics CK Subramanian, JJ Nahas US Patent 6,944,052, 2005 | 100 | 2005 |
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits X Yin, A Aziz, J Nahas, S Datta, S Gupta, M Niemier, XS Hu 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 81 | 2016 |
Demonstrated reliability of 4-Mb MRAM J Akerman, P Brown, M DeHerrera, M Durlam, E Fuchs, D Gajewski, ... IEEE Transactions on Device and Materials Reliability 4 (3), 428-435, 2004 | 80 | 2004 |
Migrating tasks between asymmetric computing elements of a multi-core processor A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ... US Patent 10,185,566, 2019 | 74* | 2019 |
Migrating tasks between asymmetric computing elements of a multi-core processor A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ... US Patent 10,185,566, 2019 | 74* | 2019 |
MRAM and methods for reading the MRAM MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ... US Patent 6,909,631, 2005 | 61 | 2005 |
MRAM and methods for reading the MRAM MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ... US Patent 6,909,631, 2005 | 61 | 2005 |
MRAM and methods for reading the MRAM MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ... US Patent 6,909,631, 2005 | 61 | 2005 |
MRAM and methods for reading the MRAM MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ... US Patent 6,909,631, 2005 | 61 | 2005 |
Modeling and computer simulation of a microwave-to-dc energy conversion element JJ Nahas IEEE Transactions on Microwave Theory and Techniques 23 (12), 1030-1035, 1975 | 58 | 1975 |
Sense amplifier for a memory having at least two distinct resistance states JJ Nahas, TW Andre, BJ Garni, CK Subramanian US Patent 6,600,690, 2003 | 50 | 2003 |
Sense amplifier for a memory having at least two distinct resistance states JJ Nahas, TW Andre, BJ Garni, CK Subramanian US Patent 6,600,690, 2003 | 50 | 2003 |
Sense amplifier for a memory having at least two distinct resistance states JJ Nahas, TW Andre, BJ Garni, CK Subramanian US Patent 6,600,690, 2003 | 50 | 2003 |