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Indranil Hatai
Indranil Hatai
Senior Application Engineer, Mathworks India Pvt Ltd
Verified email at cse.iitkgp.ernet.in
Title
Cited by
Cited by
Year
An efficient VLSI architecture of a reconfigurable pulse-shaping FIR interpolation
I Hatai, I Chakrabarti, S Banerjee
IEEE Transactions on very large scale integration (VLSI) systems 23 (6 …, 2014
512014
An efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination algorithm for reconfigurable FIR filter synthesis
I Hatai, I Chakrabarti, S Banerjee
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (4), 1071-1080, 2015
462015
A New High‐Performance Digital FM Modulator and Demodulator for Software‐Defined Radio and Its FPGA Implementation
I Hatai, I Chakrabarti
International Journal of Reconfigurable Computing 2011 (1), 342532, 2011
332011
FPGA implementation of a digital FM modem
I Hatai, I Chakrabarti
2009 International Conference on Information and Multimedia Technology, 475-479, 2009
212009
A computationally efficient reconfigurable constant multiplication architecture based on CSD decoded vertical–horizontal common sub-expression elimination algorithm
I Hatai, I Chakrabarti, S Banerjee
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (1), 130-140, 2017
182017
Reconfigurable architecture of a RRC FIR interpolator for multi-standard digital up converter
I Hatai, I Chakrabarti, S Banerjee
2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013
152013
FPGA implementation of a digital FM modem for SDR architecture
I Hatai, I Chakrabarti
2009 4th International Conference on Computers and Devices for Communication …, 2009
152009
FPGA implementation of a fetal heart rate measuring system
I Hatai, I Chakrabarti, S Banerjee
2013 2nd International Conference on Advances in Electrical Engineering …, 2013
132013
A high-speed, ROM-less DDFS for software defined radio system
I Hatai, I Chakrabarti
2010 INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING …, 2010
82010
ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm
I Hatai, R Biswas, S Banerjee
IEEE Technology Students' Symposium, 220-225, 2011
62011
A novel low-latency, high-speed DDFS architecture
I Hatai, I Chakrabarti
2010 Annual IEEE India Conference (INDICON), 1-4, 2010
42010
Parameter controlled reconfigurable baseband modulator for SDR architecture
I Hatai, I Chakrabarti
2010 2nd International Conference on Mechanical and Electronics Engineering …, 2010
32010
Design an Efficient FPGA Based Hardware Implementation for Real-Time Mobile Epileptic Seizure Prediction Using Deep Neural Network
ANU SAMANTA, I Hatai, AK Mal
22023
A Reconfigurable Gaussian Base Normalization Deep Neural Network Design for an Energy-Efficient Voice Activity Detector
A Samanta, I Hatai, AK Mal
2021 2nd International Conference on Communication, Computing and Industry 4 …, 2021
22021
Analytical Model of a Multi-Resolution Sample rate re-configurable Decimator for SDADC
A Mondal, S Bhar, S Srimani, I Hatai, K Ghosh, H Rahaman
2019 IEEE Region 10 Symposium (TENSYMP), 588-592, 2019
22019
Multi-standard programmable baseband modulator for next generation wireless communication
I Hatai, I Chakrabarti
arXiv preprint arXiv:1009.6132, 2010
22010
A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices
A Samanta, I Hatai, AK Mal
Wireless Personal Communications 137 (3), 1715-1760, 2024
12024
A Reconfigurable digital up converter architecture and its hardware Implementation for Software Defined Radio System
I Hatai
IIT, Kharagpur, 2017
12017
Programmable Common Baseband Modulator for Software Defined Radio system
I Hatai, I Chakrabarti
International Journal of Signal and Imaging Systems Engineering 4 (3), 142-152, 2011
12011
Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation
K Bhattacharyya, A Hazra, I Hatai, S Banerjee
International Journal of Signal and Imaging Systems Engineering 2 (4), 201-215, 2009
12009
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Articles 1–20