| A review on power supply induced jitter JN Tripathi, VK Sharma, H Shrimali IEEE Transactions on Components, Packaging and Manufacturing Technology 9 (3 …, 2018 | 53 | 2018 |
| Efficient modeling of power supply induced jitter in voltage-mode drivers (EMPSIJ) JN Tripathi, R Achar, R Malik IEEE Transactions on Components, Packaging and Manufacturing Technology 7 …, 2017 | 35 | 2017 |
| Efficient jitter analysis for a chain of CMOS inverters JN Tripathi, P Arora, H Shrimali, R Achar IEEE Transactions on Electromagnetic Compatibility 62 (1), 229-239, 2018 | 27 | 2018 |
| Selection and placement of decoupling capacitors in high speed systems JN Tripathi, J Mukherjee, PR Apte, NK Chhabra, RK Nagpal, R Malik IEEE Electromagnetic Compatibility Magazine 2 (4), 72-78, 2013 | 21 | 2013 |
| Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing JN Tripathi, P Damle, R Malik 2017 IEEE 21st Workshop on Signal and Power Integrity (SPI), 1-3, 2017 | 19 | 2017 |
| A comparative analysis of jitter estimation techniques VK Sharma, JN Tripathi, R Nagpal, S Deb, R Malik 2014 International Conference on Electronics, Communication and …, 2014 | 16 | 2014 |
| Optimization of analog RF circuit parameters using randomness in particle swarm optimization S Kamisetty, J Garg, JN Tripathi, J Mukherjee 2011 world congress on information and communication technologies, 274-278, 2011 | 16 | 2011 |
| An analysis of power supply induced jitter for a voltage mode driver in high speed serial links JN Tripathi, VK Sharma, H Advani, PN Singh, H Shrimali, R Malik 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), 1-4, 2016 | 15 | 2016 |
| Fast analysis of time interval error in current-mode drivers JN Tripathi, R Achar, R Malik IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (2), 367-377, 2017 | 14 | 2017 |
| Device parameter-based analytical modeling of power supply induced jitter in CMOS inverters P Arora, JN Tripathi, H Shrimali IEEE Transactions on Electron Devices 68 (7), 3268-3275, 2021 | 13 | 2021 |
| An IBIS-like modelling for power/ground noise induced jitter under simultaneous switching outputs (SSO) M Souilem, JN Tripathi, W Dghais, H Belgacem 2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI), 1-4, 2019 | 13 | 2019 |
| An efficient estimation of power supply-induced jitter by numerical method JN Tripathi, FG Canavero IEEE Microwave and Wireless Components Letters 27 (12), 1050-1052, 2017 | 13 | 2017 |
| Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms JN Tripathi, NK Chhabra, RK Nagpal, R Malik, J Mukherjee 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 361-364, 2012 | 13 | 2012 |
| Signal integrity and power integrity methodology for robust analysis of on-the-board system for high speed serial links RK Nagpal, R Malik, JN Tripathi 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 13 | 2009 |
| Optimal design of a decoupling network using variants of particle swarm optimization algorithm S Hemaram, JN Tripathi 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 10 | 2021 |
| Maintaining power integrity by damping the cavity-mode anti-resonances' peaks on a power plane by particle swarm optimization JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee Thirteenth International Symposium on Quality Electronic Design (ISQED), 525-528, 2012 | 10 | 2012 |
| Modeling the combined effects of transmission media and ground bounce on power supply induced jitter JN Tripathi, A Javaid, R Achar IEEE Transactions on Electromagnetic Compatibility 61 (4), 1183-1190, 2018 | 9 | 2018 |
| A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits JN Tripathi, J Mukherjee, PR Apte, RK Nagpal, NK Chhabra, R Malik 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging …, 2013 | 9 | 2013 |
| Device parameters based analytical modeling of ground-bounce induced jitter in CMOS inverters VK Verma, JN Tripathi IEEE Transactions on Electron Devices 69 (10), 5462-5469, 2022 | 8 | 2022 |
| Signal integrity and power integrity issues at system level JN Tripathi, RK Nagpal, R Malik IETE Technical Review 29 (5), 365-371, 2012 | 8 | 2012 |
Hitesh ShrimaliAssociate Professor, IIT MandiVerified email at iitmandi.ac.in
