Sanket Tavarageri
Title
Cited by
Cited by
Year
Parameterized tiling revisited
MM Baskaran, A Hartono, S Tavarageri, T Henretty, J Ramanujam, ...
Proceedings of the 8th annual IEEE/ACM international symposium on Code …, 2010
882010
Dynamic selection of tile sizes
S Tavarageri, LN Pouchet, J Ramanujam, A Rountev, P Sadayappan
2011 18th International Conference on High Performance Computing, 1-10, 2011
322011
Parametric tiling of affine loop nests
S Tavarageri, A Hartono, M Baskaran, LN Pouchet, J Ramanujam, ...
Proc. 15th Workshop on Compilers for Parallel Computers. Vienna, Austria, 2010
312010
Pwcet: Power-aware worst case execution time analysis
W Bao, S Tavarageri, F Ozguner, P Sadayappan
2014 43rd International Conference on Parallel Processing Workshops, 439-447, 2014
202014
A compiler analysis to determine useful cache size for energy efficiency
S Tavarageri, P Sadayappan
2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013
152013
Compiler-assisted detection of transient memory errors
S Tavarageri, S Krishnamoorthy, P Sadayappan
Proceedings of the 35th ACM SIGPLAN Conference on Programming Language …, 2014
112014
A tale of three runtimes
N Vasilache, M Baskaran, T Henretty, B Meister, MH Langston, ...
arXiv preprint arXiv:1409.1914, 2014
92014
Adaptive parallel tiled code generation and accelerated auto-tuning
S Tavarageri, J Ramanujam, P Sadayappan
The International journal of high performance computing applications 27 (4 …, 2013
72013
Compiler support for software cache coherence
S Tavarageri, W Kim, J Torrellas, P Sadayappan
2016 IEEE 23rd International Conference on High Performance Computing (HiPC …, 2016
62016
A medical price prediction system using hierarchical decision trees
A Tike, S Tavarageri
2017 IEEE International Conference on Big Data (Big Data), 3904-3913, 2017
42017
A Data Analytics Framework for Aggregate Data Analysis
S Tavarageri, N Mani, A Ramasubramanian, J Kalsi
arXiv preprint arXiv:1809.05877, 2018
12018
Architecting and programming a hardware-incoherent multiprocessor cache hierarchy
W Kim, S Tavarageri, P Sadayappan, J Torrellas
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2016
12016
Automatic cluster parallelization and minimizing communication via selective data replication
S Tavarageri, B Meister, M Baskaran, B Pradelle, T Henretty, ...
2015 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2015
12015
Automatic code generation for an asynchronous task-based runtime
M Baskaran, B Meister, T Henretty, S Tavarageri, B Pradelle, ...
RESPA Workshop, co-located with SC 15, 2015
12015
Automatic Generation of Coherence Instructions for Software-Managed Multiprocessor Caches
S Tavarageri, W Kim, J Torrellas, P Sadayappan
submission, 0
1
SYSTEMS AND METHODS FOR EFFICIENT TARGETING
T Henretty, A Johnson, A Konstantinidis, JO Mcmahon, BJ Meister, ...
US Patent App. 16/653,201, 2020
2020
SYSTEMS AND METHODS FOR MINIMIZING COMMUNICATIONS
T Henretty, A Johnson, A Konstantinidis, JO Mcmahon, BJ Meister, ...
US Patent App. 16/700,331, 2020
2020
PolyDL: Polyhedral Optimizations for Creation of High Performance DL primitives
S Tavarageri, A Heinecke, S Avancha, G Goyal, R Upadrasta, B Kaul
arXiv preprint arXiv:2006.02230, 2020
2020
PolyScientist: Automatic Loop Transformations Combined with Microkernels for Optimization of Deep Learning Primitives
S Tavarageri, A Heinecke, S Avancha, G Goyal, R Upadrasta, B Kaul
arXiv preprint arXiv:2002.02145, 2020
2020
Systems and methods for energy proportional scheduling
MM Baskaran, T Henretty, A Johnson, A Konstantinidis, MH Langston, ...
US Patent 10,540,107, 2020
2020
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