| Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance V Kumari, N Modi, M Saxena, M Gupta IEEE transactions on electron devices 62 (7), 2098-2105, 2015 | 39 | 2015 |
| Two-dimensional analytical drain current model for double-gate MOSFET incorporating dielectric pocket V Kumari, M Saxena, RS Gupta, M Gupta IEEE transactions on electron devices 59 (10), 2567-2574, 2012 | 39 | 2012 |
| Modeling and simulation of double gate junctionless transistor considering fringing field effects V Kumari, N Modi, M Saxena, M Gupta Solid-State Electronics 107, 20-29, 2015 | 29 | 2015 |
| Empirical model for nonuniformly doped symmetric double-gate junctionless transistor V Kumari, A Kumar, M Saxena, M Gupta IEEE transactions on Electron Devices 65 (1), 314-321, 2017 | 27 | 2017 |
| Impact of heavy ion particle strike induced single event transients on conventional and π-Gate AlGaN/GaN HEMTs K Sehra, V Kumari, M Gupta, M Mishra, DS Rawal, M Saxena Semiconductor Science and Technology 36 (3), 035009, 2021 | 21 | 2021 |
| Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior V Kumari, A Kumar, M Saxena, M Gupta Superlattices and Microstructures 113, 57-70, 2018 | 18 | 2018 |
| Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range V Kumari, M Saxena, RS Gupta, M Gupta Microelectronics Reliability 52 (6), 974-983, 2012 | 18 | 2012 |
| Analytical Modeling of Dielectric Pocket Double Gate (DP-DG) MOSFET Incorporating Hot Carrier Induced Interface Charges MG Vandana Kumari, Manoj Saxena, R.S. Gupta IEEE Transactions on Device and Material Reliability 14 (1), 390-399, 0 | 17* | |
| Nanoscale-RingFET: an analytical drain current model including SCEs S Kumar, V Kumari, S Singh, M Saxena, M Gupta IEEE Transactions on Electron Devices 62 (12), 3965-3972, 2015 | 15 | 2015 |
| TCAD-based optimization of field plate length & passivation layer of AlGaN/GaN HEMT for higher cut-off frequency & breakdown voltage Neha, V Kumari, M Gupta, M Saxena IETE Technical Review 39 (1), 63-71, 2022 | 13 | 2022 |
| TCAD-based investigation of double gate JunctionLess transistor for UV photodetector V Kumari, M Gupta, M Saxena IEEE Transactions on Electron Devices 68 (6), 2841-2847, 2021 | 13 | 2021 |
| Optimization of π–gate AlGaN/AlN/GaN HEMTs for low noise and high gain applications K Sehra, V Kumari, M Gupta, M Mishra, DS Rawal, M Saxena Silicon, 1-12, 2020 | 12 | 2020 |
| Optimization of asymmetric π Gate HEMT for improved reliability & frequency applications K Sehra, V Kumari, V Nath, M Gupta, M Saxena 2019 IEEE 9th International Nanoelectronics Conferences (INEC), 1-4, 2019 | 12 | 2019 |
| TCAD based investigation of single event transient effect in double channel AlGaN/GaN HEMT S Das, V Kumari, K Sehra, M Gupta, M Saxena IEEE Transactions on Device and Materials Reliability 21 (3), 416-423, 2021 | 11 | 2021 |
| A Π-shaped p-GaN HEMT for reliable enhancement mode operation K Sehra, V Kumari, M Gupta, M Mishra, DS Rawal, M Saxena Microelectronics Reliability 133, 114544, 2022 | 10 | 2022 |
| TCAD investigation of gate-lag measurements on conventional and π-gate AlGaN/GaN HEMTs K Sehra, V Kumari, M Gupta, M Mishra, DS Rawal, M Saxena 2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO), 128-133, 2020 | 10 | 2020 |
| Simulation study of insulated shallow extension silicon on Nothing (ISESON) MOSFET for high temperature applications V Kumari, M Saxena, RS Gupta, M Gupta Microelectronics Reliability 52 (8), 1610-1612, 2012 | 10 | 2012 |
| Comparison of linearity and intermodulation distortion metrics for T-and Pi-gate HEMT K Sehra, V Kumari, V Nath, M Gupta, DS Rawal, M Saxena 2019 International Conference on Electrical, Electronics and Computer …, 2019 | 8 | 2019 |
| Sub-threshold drain current model of double gate RingFET (DG-RingFET) architecture: an analog and linearity performance investigation for RFIC design S Kumar, V Kumari, S Singh, M Saxena, M Gupta IETE Technical Review 35 (2), 169-179, 2018 | 8 | 2018 |
| Underlapped FinFET on insulator: Quasi3D analytical model V Kumari, K Sharmetha, M Saxena, M Gupta Solid-State Electronics 129, 138-149, 2017 | 7 | 2017 |
KHUSHWANT SEHRADepartment of Electronic Science, University of DelhiVerified email at ddu.du.ac.in
