| Performance analysis of gate electrode work function variations in double-gate junctionless FET S Kumar, AK Chatterjee, R Pandey Silicon 13, 3447-3459, 2021 | 22 | 2021 |
| Analysis, verification and FPGA implementation of Vedic Multiplier with BIST capability V Kumar, AKG Chatterjee | 10 | 2009 |
| Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs M Bhartia, AK Chatterjee Journal of Semiconductors 36 (4), 044003, 2015 | 9 | 2015 |
| Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool S Kumar, AK Chatterjee, R Pandey Journal of Computational Electronics 20, 2317-2330, 2021 | 8 | 2021 |
| Analytical Model for Drain Current of a Ballistic MOSFET AK Chatterjee, M Kushwaha, B Prasad Silicon 13, 1777-1785, 2021 | 4 | 2021 |
| Study of ground plane FD SOI structures at 25 nm A Singh, AK Chatterjee International Conference on Nanoscience, Engineering and Technology (ICONSET …, 2011 | 4 | 2011 |
| Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application S Kumar, AK Chatterjee, R Pandey Semiconductor Science and Technology 37 (4), 045017, 2022 | 3 | 2022 |
| Generalized Analytical Approach for Estimating the Wave function and Gate Tunneling Current in a Nanoscale MOSFET M Kushwaha, AK Chatterjee, B Prasad IEEE International Conference on Emerging Electronics (ICEE), 2014 | 3 | 2014 |
| Design of low power and high speed sense amplifier AKG Chatterjee | 3 | 2010 |
| Development of Biofilm Nanowires and Electrode for Efficient Microbial Fuel Cells (MFCs) A Kodesia, MG Ghosh, AG Chatterjee | 2 | 2017 |
| Design and Analysis of Recessed Double Gate Junctionless Field-Effect-Transistor Based Digital Standard Cells S Kumar, AK Chatterjee, R Pandey Silicon 14 (17), 11323-11335, 2022 | 1 | 2022 |
| Design and Verification of nMOSFET for Low Leakage at 90nm Process Technology P Trivedi, AK Chatterjee, HR Gupta 2013 International Conference on Communication Systems and Network …, 2013 | 1 | 2013 |
| Modelingof Drain Current for Lightly Doped Symmetrical Double Gate MOSFETIncluding Short Channel Effects AKC Mini Bhartia Thapar University, Patiala, Punjab, India, 2015 | | 2015 |
| Modelling of Direct Tunnelling Gate Leakage Current through High-k/SiO2 Gate Stacks Shrutika Satyanarayana, .Arun Kumar Chatterjee Thapar University, Patiala, Punjab, India, 2015 | | 2015 |
| Modelingof Drain Current for Lightly Doped Symmetrical Double Gate MOSFETIncluding Short Channel Effects M Bhartia, AKG Chatterjee | | 2014 |
| Design And Analysis of Nanocrystal Flash Memory Cell Based on Single Gate and Double Gate Mosfet Strutures A Singla, AKG Chatterjee | | 2014 |
| DESIGN, ANALYSIS AND SIMULATION OF SINGLE AND MULTIFIN TRIGATE FinFET STRUCTURE AND CMOS IMPLEMENTATION OF FinFETs AKC Shivam Shrivastava Thapar University, Patiala, Punjab, India, 2014 | | 2014 |
| Design of 45 nm Fully Depleted Double Gate SOI MOSFET AKC Mini Bhartia, Shrutika . Satyanarayana International Journal of Engineering Research & Technology 3 (Issue 2), 1973 …, 2014 | | 2014 |
| Design of high speed and low power SRAM decoder S Jain, AKG Chatterjee | | 2013 |
| Design of a high speed and low power sense amplifier AKC Sunil Kumar Thapar University, Patiala, Punjab, India, 2013 | | 2013 |
Dr. RISHIKESH PANDEYThapar University, PatialaVerified email at thapar.edu
