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Nagendra Gulur
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Rethinking TLB designs in virtualized environments: A very large part-of-memory TLB
JH Ryoo, N Gulur, S Song, LK John
ACM SIGARCH Computer Architecture News 45 (2), 469-480, 2017
852017
Bi-modal dram cache: Improving hit rate, hit latency and bandwidth
N Gulur, M Mehendale, R Manikantan, R Govindarajan
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 38-50, 2014
672014
CSALT: Context switch aware large TLB
Y Marathe, N Gulur, JH Ryoo, S Song, LK John
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
392017
Multiple sub-row buffers in dram: Unlocking performance and energy improvement opportunities
ND Gulur, R Manikantan, M Mehendale, R Govindarajan
Proceedings of the 26th ACM international conference on Supercomputing, 257-266, 2012
362012
Anatomy: An analytical model of memory system performance
N Gulur, M Mehendale, R Manikantan, R Govindarajan
ACM SIGMETRICS Performance Evaluation Review 42 (1), 505-517, 2014
222014
A comprehensive analytical performance model of dram caches
N Gulur, M Mehendale, R Govindarajan
Proceedings of the 6th ACM/SPEC International Conference on Performance …, 2015
92015
Bi-modal dram cache: A scalable and effective die-stacked dram cache
N Gulur, M Mehendale, R Manikantan, R Govindarajan
Proceedings of the 47th Annual IEEE/ACM International Symposium on …, 2014
82014
MicroRefresh: Minimizing refresh overhead in DRAM caches
N Gulur, R Govindarajan, M Mehendale
Proceedings of the Second International Symposium on Memory Systems, 350-361, 2016
72016
Row-buffer reorganization: simultaneously improving performance and reducing energy in drams
N Gulur, R Manikantan, R Govindarajan, M Mehendale
2011 International Conference on Parallel Architectures and Compilation …, 2011
62011
Express: Simultaneously achieving storage, execution and energy efficiencies in moderately sparse matrix computations
S Adavally, N Gulur, K Kavi, A Weaver, P Dutta, B Wang
The International Symposium on Memory Systems, 46-60, 2020
52020
Heterogeneous architecture for sparse data processing
S Adavally, A Weaver, P Vasireddy, K Kavi, G Mehta, N Gulur
2022 IEEE International Parallel and Distributed Processing Symposium …, 2022
22022
CHASM: Security Evaluation of Cache Mapping Schemes
F Mosquera, N Gulur, K Kavi, G Mehta, H Sun
Embedded Computer Systems: Architectures, Modeling, and Simulation: 20th …, 2020
22020
Understanding the Performance Benefit of Asynchronous Data Transfers in OpenCL Programs Executing on Media Processors
N Gulur, NL Suriya
2015 IEEE 22nd International Conference on High Performance Computing (HiPC …, 2015
22015
ATTC (@ C) Addressable-TLB based Translation Coherence
H Gugale, N Gulur, Y Marathe, LK John
Proceedings of the ACM International Conference on Parallel Architectures …, 2020
12020
Method to determine contrariety between architectures containing stratified memory mapped register sets
V Easwaran, N Gulur, S Srirangapathi, M Mody, R Gulati, P Karandikar, ...
2014 Fifth International Symposium on Electronic System Design, 210-214, 2014
12014
CSALT
Y Marathe, N Gulur, JH Ryoo, S Song, LK John
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
2017
Multiple sub-row buffers in DRAM
ND Gulur, R Manikantan, M Mehendale, R Govindarajan
Proceedings of the 26th ACM international conference on Supercomputing, 2012
2012
IPDPSW 2022
RD Friese, JK Kim, B Shirazi, L White, S Adavally, A Weaver, G Mehta, ...
A Technique for Improving Performance of Moderately Sparse Matrix Algorithms
S Adavally, K Kavi, N Gulur
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