Dr. Parameshwara MC
Dr. Parameshwara MC
Vemana Institute of Technology
Verified email at vemanait.edu.in
Title
Cited by
Cited by
Year
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications
MC Parameshwara, HC Srinivasaiah
Journal of Circuits, Systems and Computers 26 (01), 1750014, 2017
222017
Approximate Full Adders for Energy Efficient Image Processing Applications
MC Parameshwara
Journal of Circuits, Systems and Computers, 2150235, 2021
22021
A Novel Low Power 1-bit Full Adder with CMOS Transmission-gate Architecture for Portable Application
MC Parameshwara, KS Shashidhara, S HC
Proc. of Emerging Research in Computing, Information, Communication and …, 2013
22013
Approximate Full Adders for Multimedia Processing Applications
CV Gowdar, MC Parameshwara, S Sonoli
2020 IEEE International Conference for Innovation in Technology (INOCON), 1-4, 2020
12020
COMPARATIVE ANALYSIS OF VARIOUS APPROXIMATE FULL ADDERS UNDER RTL CODES
CV Gowdar, MC Parameshwara, S Sonoli
Journal on Microelectronics 6 (2), 947-952, 2020
12020
Partial Product Compression Methods: A Study and Performance Comparison Using a Tree Structured Multipliers
MC Parameshwara, HC Srinivasaiah
International Journal of Engineering Research and General Science 4 (2), 749-756, 2016
12016
Choice of Adders for Multimedia Processing Applications: Comparison of Various Existing and a Novel 1-Bit Full Adder
MC Parameshwara, HC Srinivasaiah
12015
Novel low quantum cost reversible logic based full adders for DSP applications
MC Parameshwara, M Nagabushanam
International Journal of Information Technology, 1-7, 2021
2021
ROBUST AND SCALABLE HYBRID 1-BIT FULL ADDER CIRCUIT FOR VLSI APPLICATIONS
MC Parameshwara
Journal on Microelectronics 7 (2), 1109-1114, 2021
2021
DESIGN OF ENERGY EFFICIENT APPROXIMATE MULTIPLIERS FOR IMAGE PROCESSING APPLICATIONS
CV Gowdar, MC Parameshwara
Journal on Microelectronics 7 (1), 1057-1061, 2021
2021
DESIGN OF CARRY DEPENDENT SUM ADDER USING REVERSIBLE LOGIC
MC Parameshwara
Journal on Microelectronics 6 (3), 964-969, 2020
2020
Low Power and Area Efficient Phase Accumulator for DDFS Applications
MC Parameshwara
2018 15th IEEE India Council International Conference (INDICON), 2020
2020
Performance Comparison of 1-bit Full Adders using 180 nm CMOS Technology
Bhagyashree, KS Shashidhara, MC Parameshwara
International Journal of Engineering Development and Research 7 (3), 86-90, 2019
2019
Design, Implementation and Analysis of Error Tolerant Adder in CMOS 180nm Technology
MC Kusumitha, KS Shashidhara, MC Parameshwara
International Journal of Engineering Development and Research 7 (3), 23-27, 2019
2019
Text Image to Braille Code Converter
Shwethashree S, Sowmya S K, Sri Ranjini, Vanaja N, MC Parameshwara
International Journal of Engineering Research in Electronics and …, 2018
2018
Study of spectral purity dependence on sine-ROM size in a digitally controlled frequency synthesizer
MC Parameshwara, HC Srinivasaiah
2017 International Conference on Wireless Communications, Signal Processing …, 2017
2017
Sine linear-phase-offset difference method: A novel approach for sine ROM compression
MC Parameshwara, HC Srinivasaiah
2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016
2016
A Novel ROM based DDFS Architecture for Portable and Wide band Communication
MC Parameshwara, HC Srinivasaiah
International Journal of Engineering Research and General Science 3 (5), 509-516, 2015
2015
Study of power-delay characteristics of a mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length
MC Parameshwara, HC Srinivasaiah
International Journal of Computer Applications 119 (4), 2015
2015
Empirical Model Based Variability Analysis of Terminal Currents of MOSFET of a 65nm SRAM Cell in Process-Voltage-Temperature (PVT) Space
GVM MC Parameshwara, KS Shashidhara, HC Srinivasaiah
IJERT 3 (3), 2014
2014
The system can't perform the operation now. Try again later.
Articles 1–20