| Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs SP Scarlet, R Ambika, R Srinivasan Superlattices and Microstructures 107, 178-188, 2017 | 14 | 2017 |
| Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering SP Scarlet, R Srinivasan Materials Science in Semiconductor Processing 84, 107-114, 2018 | 7 | 2018 |
| Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations P Scarlet, KK Nagarajan, R Srinivasan 2013 International Conference on Circuits, Power and Computing Technologies …, 2013 | 4 | 2013 |
| Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering SP Scarlet, N Vinodhkumar, R Srinivasan Journal of Computational Electronics 20, 209-217, 2021 | 2 | 2021 |
| Nanoscale junctionless devices using ringFET structure on bulk silicon substrate SP Scarlet, R Srinivasan, P Sasikala International Journal of Electronics Letters 6 (4), 468-480, 2018 | 1 | 2018 |
| Impact of Doping and Spacer on the Performance of Bulk Planar Junctionless devices SP Scarlet, R Srinivasan 2018 4th International Conference on Electrical Energy Systems (ICEES), 267-273, 2018 | 1 | 2018 |
| Performance optimisation of junctionless FET in nano regime using segmented channel-A 3D numerical simulation study SP Scarlet, B Prasannanjaneyulu, R Srinivasan Superlattices and Microstructures 111, 1233-1243, 2017 | 1 | 2017 |
| Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation P Sasikala, P Scarlet, KK Nagarajan | | |
