| Filter optimization for grid interactive voltage source inverters P Channegowda, V John IEEE Transactions on Industrial Electronics 57 (12), 4106-4114, 2010 | 434 | 2010 |
| High-performance active gate drive for high-power IGBT's V John, BS Suh, TA Lipo IEEE Transactions on Industry Applications 35 (5), 1108-1117, 1999 | 232 | 1999 |
| Investigation of antiislanding protection of power converter based distributed generators using frequency domain analysis V John, Z Ye, A Kolwalkar 2003 IEEE Power Engineering Society General Meeting (IEEE Cat. No. 03CH37491 …, 2003 | 178 | 2003 |
| Mitigation of Lower Order Harmonics in a Grid Connected Single Phase PV Inverter VJ A Kulkarni IEEE Transactions on Power Electronics 2, 2013 | 161 | 2013 |
| Northern Power Systems WindPACT drive train alternative design study report G Bywaters, V John, J Lynch, P Mattila, G Norton, J Stowell, M Salata, ... NREL, Golden, Colorado, Report No. NREL/SR-500-35524, 2004 | 152 | 2004 |
| Common-mode filter design for PWM rectifier-based motor drives MH Hedayati, AB Acharya, V John IEEE Transactions on Power electronics 28 (11), 5364-5371, 2013 | 122 | 2013 |
| Dynamic modeling and analysis of buck converter based solar PV charge controller for improved MPPT performance D Venkatramanan, V John IEEE Transactions on Industry Applications 55 (6), 6234-6246, 2019 | 121 | 2019 |
| Fast-clamped short-circuit protection of IGBT's V John, BS Suh, TA Lipo IEEE Transactions on Industry Applications 35 (2), 477-486, 1999 | 97 | 1999 |
| A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion A Kulkarni, V John IECON 2013-39th Annual Conference of the IEEE Industrial Electronics Society …, 2013 | 94 | 2013 |
| Anti-windup Schemes for Proportional Integral and Proportional Resonant Controller. A Ghoshal, V John Indian Institute of Technology Roorkee., 2010 | 87 | 2010 |
| A method to improve PLL performance under abnormal grid conditions A Ghoshal, V John Proc. NPEC 7, 17-19, 2007 | 83 | 2007 |
| Design of a fast response time single-phase PLL with DC offset rejection capability A Kulkarni, V John Electric Power Systems Research 145, 35-43, 2017 | 80 | 2017 |
| A novel method for measuring induction machine magnetizing inductance AV Stankovic, EL Benedict, V John, TA Lipo IEEE Transactions on Industry Applications 39 (5), 1257-1263, 2003 | 79 | 2003 |
| Analysis of bandwidth–unit-vector-distortion tradeoff in PLL during abnormal grid conditions A Kulkarni, V John IEEE Transactions on Industrial Electronics 60 (12), 5820-5829, 2012 | 77 | 2012 |
| Analysis and design of split‐capacitor resistive‐inductive passive damping for LCL filters in grid‐connected inverters AK Balasubramanian, V John IET Power Electronics 6 (9), 1822-1832, 2013 | 74 | 2013 |
| Short circuit protection of IGBTs and other power switching devices V John, BS Suh, TA Lipo US Patent 6,097,582, 2000 | 68 | 2000 |
| Method and apparatus for anti-islanding protection of distributed generations Z Ye, V John, C Wang, LJ Garces, R Zhou, L Li, RA Walling, ... US Patent 7,016,793, 2006 | 65 | 2006 |
| Active damping of LCL filter at low switching to resonance frequency ratio A Ghoshal, V John IET Power Electronics 8 (4), 574-582, 2015 | 64 | 2015 |
| Dynamic phasor modeling and stability analysis of SRF-PLL-based grid-tie inverter under islanded conditions D Venkatramanan, V John IEEE Transactions on Industry Applications 56 (2), 1953-1965, 2019 | 63 | 2019 |
| Design of synchronous reference frame phase‐locked loop with the presence of dc offsets in the input voltage A Kulkarni, V John IET Power Electronics 8 (12), 2435-2443, 2015 | 57 | 2015 |
D VenkatramananAssistant Professor, Indian Institute of Technology Bombay (IITB)Verified email at iitb.ac.in
