Niladrish Chatterjee
Niladrish Chatterjee
NVIDIA Research
Verified email at nvidia.com - Homepage
Title
Cited by
Cited by
Year
Rethinking DRAM design and organization for energy-constrained multi-cores
AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ...
Proceedings of the 37th annual international symposium on Computer …, 2010
3012010
Micro-pages: increasing DRAM efficiency with locality-aware data placement
K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ...
ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010
2662010
Usimm: the utah simulated memory module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
University of Utah, Tech. Rep, 1-24, 2012
172*2012
Transparent offloading and mapping (TOM) enabling programmer-transparent near-data processing in GPU systems
K Hsieh, E Ebrahimi, G Kim, N Chatterjee, M O'Connor, N Vijaykumar, ...
ACM SIGARCH Computer Architecture News 44 (3), 204-216, 2016
1572016
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ...
Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017
1052017
Managing DRAM latency divergence in irregular GPGPU applications
N Chatterjee, M O'Connor, GH Loh, N Jayasena, R Balasubramonia
SC'14: Proceedings of the International Conference for High Performance …, 2014
772014
Leveraging heterogeneity in DRAM main memories to accelerate critical word access
N Chatterjee, M Shevgoor, R Balasubramonian, A Davis, Z Fang, R Illikkal, ...
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 13-24, 2012
742012
Compressing DMA engine: Leveraging activation sparsity for training deep neural networks
M Rhu, M O'Connor, N Chatterjee, J Pool, Y Kwon, SW Keckler
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
732018
Staged reads: Mitigating the impact of DRAM writes on DRAM reads
N Chatterjee, N Muralimanohar, R Balasubramonian, A Davis, NP Jouppi
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
682012
Anatomy of gpu memory system for multi-application execution
A Jog, O Kayiran, T Kesten, A Pattnaik, E Bolotin, N Chatterjee, ...
Proceedings of the 2015 International Symposium on Memory Systems, 223-234, 2015
662015
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems
M O’Connor, N Chatterjee, D Lee, J Wilson, A Agrawal, SW Keckler, ...
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017
602017
Architecting an energy-efficient DRAM system for GPUs
N Chatterjee, M O’Connor, D Lee, DR Johnson, SW Keckler, M Rhu, ...
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
532017
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
M Shevgoor, JS Kim, N Chatterjee, R Balasubramonian, A Davis, ...
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
512013
What your DRAM power models are not telling you: Lessons from a detailed experimental study
S Ghose, AG Yaglikçi, R Gupta, D Lee, K Kudrolli, WX Liu, H Hassan, ...
Proceedings of the ACM on Measurement and Analysis of Computing Systems 2 (3 …, 2018
482018
Page migration in a 3D stacked hybrid memory
NS Jayasena, GH Loh, JM O'connor, N Chatterjee
US Patent 9,535,831, 2017
302017
Memory access methods and apparatus
N Muralimanohar, AN Udipi, N Chatterjee, R Balasubramonian, AL Davis, ...
US Patent 9,361,955, 2016
282016
Toward standardized near-data processing with unrestricted data placement for GPUs
G Kim, N Chatterjee, M O'Connor, K Hsieh
Proceedings of the International Conference for High Performance Computing …, 2017
192017
Memory access methods and apparatus
N Muralimanohar, AN Udipi, N Chatterjee, R Balasubramonian, AL Davis, ...
US Patent 9,846,550, 2017
162017
Page migration in a hybrid memory device
NS Jayasena, GH Loh, JM O'connor, N Chatterjee
US Patent 9,910,605, 2018
132018
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization
KK Chang, AG Yaglikci, A Agrawal, N Chatterjee, S Ghose, A Kashyap, ...
Analysis, and Mechanisms. In SIGMETRICS 3 (5.5), 3.5, 2017
132017
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