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Abdul Majeed K K
Abdul Majeed K K
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Title
Cited by
Cited by
Year
Low power, high frequency, free dead zone PFD for a PLL design
KKA Majeed, BJ Kailath
2013 IEEE Faible Tension Faible Consommation, 1-4, 2013
322013
A novel phase frequency detector for a high frequency PLL design
KKA Majeed, BJ Kailath
Procedia Engineering 64, 377-384, 2013
282013
Underwater wireless optical communication systems: A survey
PK Sajmath, RV Ravi, KKA Majeed
2020 7th International Conference on Smart Structures and Systems (ICSSS), 1-7, 2020
112020
Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP
KK Abdul Majeed, BJ Kailath
Analog Integrated Circuits and Signal Processing 93 (1), 29-39, 2017
92017
Analysis and design of low power nonlinear PFD architectures for a fast locking PLL
KKA Majeed, BJ Kailath
2016 IEEE Students’ Technology Symposium (TechSym), 136-140, 2016
72016
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur
AMK Kuppalath, BJ Kailath
IEICE Electronics Express 13 (10), 20160328-20160328, 2016
62016
CMOS current starved voltage controlled oscillator circuit for a fast locking PLL
AM KK, BJ Kailath
2015 Annual IEEE India Conference (INDICON), 1-5, 2015
62015
PLL architecture with a composite PFD and variable loop filter
AM KK, BJ Kailath
IET Circuits, Devices & Systems 12 (3), 256-262, 2018
42018
Analysis of static noise margin of 10T SRAM using sleepy stack transistor approach
U Nanda, D Nayak, SK Saw, AM KK, B Jena
2021 Devices for Integrated Circuit (DevIC), 242-246, 2021
22021
Diagnosis of fetal arrhythmia using JADE algorithm
K Surya, KKA Majeed, RV Ravi
2020 7th International Conference on Smart Structures and Systems (ICSSS), 1-5, 2020
22020
Composite PFD based low-power, low noise, fast lock-in PLL
BJ Kailath, KKA Majeed
VLSI and Post-CMOS Electronics: Design, modelling and simulation 1, 135, 2019
12019
Safeguarding railway communication signals from radiated intentional EMI from a train
S Biju, KK Majeed, RV Ravi
International Journal of Information Technology 13 (3), 973-981, 2021
2021
Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur
R Singh, KK Majeed, U Nanda
International Conference on Microelectronic Devices, Circuits and Systems …, 2021
2021
Multichannel Probabilistic Framework for Prenatal Diagnosis of Fetal Arrhythmia Using ECG
K Surya, KK Abdul Majeed
Second International Conference on Networks and Advances in Computational …, 2021
2021
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