Abdul Majeed K K
Abdul Majeed K K
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Low power, high frequency, free dead zone PFD for a PLL design
KKA Majeed, BJ Kailath
2013 IEEE Faible Tension Faible Consommation, 1-4, 2013
A novel phase frequency detector for a high frequency PLL design
KKA Majeed, BJ Kailath
Procedia Engineering 64, 377-384, 2013
Underwater wireless optical communication systems: A survey
PK Sajmath, RV Ravi, KKA Majeed
2020 7th international conference on smart structures and systems (ICSSS), 1-7, 2020
Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP
KK Abdul Majeed, BJ Kailath
Analog Integrated Circuits and Signal Processing 93, 29-39, 2017
PLL architecture with a composite PFD and variable loop filter
AM KK, BJ Kailath
IET Circuits, Devices & Systems 12 (3), 256-262, 2018
CMOS current starved voltage controlled oscillator circuit for a fast locking PLL
AM KK, BJ Kailath
2015 Annual IEEE India Conference (INDICON), 1-5, 2015
Analysis and design of low power nonlinear PFD architectures for a fast locking PLL
KKA Majeed, BJ Kailath
2016 IEEE Students’ Technology Symposium (TechSym), 136-140, 2016
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur
AMK Kuppalath, BJ Kailath
IEICE Electronics Express 13 (10), 20160328-20160328, 2016
Diagnosis of fetal arrhythmia using JADE algorithm
K Surya, KKA Majeed, RV Ravi
2020 7th International Conference on Smart Structures and Systems (ICSSS), 1-5, 2020
Multichannel probabilistic framework for prenatal diagnosis of fetal arrhythmia using ECG
K Surya, KK Abdul Majeed
Second International Conference on Networks and Advances in Computational …, 2021
Design and Implementation of Transmission Gate based VCO Architectures for Better Performance
ES Jesseca, KKA Majeed, V Vijayvargiya
2022 7th International Conference on Communication and Electronics Systems …, 2022
Analysis of static noise margin of 10T SRAM using sleepy stack transistor approach
U Nanda, D Nayak, SK Saw, AM KK, B Jena
2021 Devices for Integrated Circuit (DevIC), 242-246, 2021
Composite PFD based low-power, low noise, fast lock-in PLL
BJ Kailath, KKA Majeed
VLSI and Post-CMOS Electronics: Design, modelling and simulation 1, 135, 2019
A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis and Future Trends
IEEE Access 11 (2023), 127987-128017, 2023
Safeguarding railway communication signals from radiated intentional EMI from a train
S Biju, KKA Majeed, RV Ravi
International Journal of Information Technology 13 (3), 973-981, 2021
Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur
R Singh, KKA Majeed, U Nanda
Microelectronic Devices, Circuits and Systems: Second International …, 2021
Phase Frequency Detector using PLL for High Frequencies
SNV Vetukuri, KKA Majeed
2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 1-4, 2023
Detection, Classification and Counting RBCs and WBCs Using Deep Learning
Y Gangula, AM K K
2023 Third International Conference on Secure Cyber Computing and …, 2023
Composite PFD based Low Power Low Noise Fast Locking PLL with Dynamic Loop Bandwidth
Chennai, 0
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