| Impulse noise classification using machine learning classifier and robust statistical features K Kunaraj, S Maria Wenisch, S Balaji, FP Mahimai Don Bosco Computational Vision and Bio-Inspired Computing: ICCVBIC 2019, 631-644, 2020 | 8 | 2020 |
| 0.35 µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops S Balaji, VB Chandratre, M Tewani 21st International Conference on VLSI Design (VLSID 2008), 613-619, 2008 | 8 | 2008 |
| Single-Event-Hardened All-Digital Delay Generator for FPGA-Based Implementation of a TDC-based readout electronics S Balaji, S Ramasamy Journal of Instrumentation 12 (09), C09007, 2017 | 4 | 2017 |
| Low voltage CMOS timing generator using array of digital delay lock loops S Balaji, KS Srinivasan 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 3 | 2012 |
| Clock generation using delay lock loop with dual control for PET/CT S Senthilnathan, S Balaji, R Prithiviraj 2013 International Conference on Advanced Electronic Systems (ICAES), 98-102, 2013 | 2 | 2013 |
| An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops B Srinivasan, VB Chandratre 2010 23rd International Conference on VLSI Design, 335-338, 2010 | 2 | 2010 |
| Modeling of Diabetic Retinopathy Grading Using Deep Learning B Srinivasan, P Rajalingam, AJ Arokiachamy Simulation and Analysis of Mathematical Methods in Real‐Time Engineering …, 2021 | 1 | 2021 |
| Single-Event-Hardened Timing Generator for waveform digitizer based readout electronics S Balaji, D Meganathan, S Ramasamy Journal of Instrumentation 14 (06), C06021, 2019 | 1 | 2019 |
| Error Correction Circuit for Single-Event Hardening of Delay Locked Loops S Balaji, S Ramasamy Circuits and Systems 7 (9), 2437-2442, 2016 | 1 | 2016 |
| Impact of radiation-induced single-event transients on high resolution time to digital converter S Balaji, S Ramasamy 2015 15th European Conference on Radiation and Its Effects on Components and …, 2015 | 1 | 2015 |
| Low power 10T phase and frequency detector for high frequency phase locked loop P Rajalingam, B Srinivasan, S Jayakumar, S Routray International Journal of Numerical Modelling: Electronic Networks, Devices …, 2024 | | 2024 |
| Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier B Srinivasan, P Rajalingam, S Routray AEU-International Journal of Electronics and Communications 154, 154315, 2022 | | 2022 |
| Automated Early Prediction of Anomalies Due to Diabetes Using Fundus Images SD Sivakumar, V Seenuvasan, B Gunasri, B Srinivasan Integrating AI in IoT Analytics on the Cloud for Healthcare Applications …, 2022 | | 2022 |
| FPGA accelerated computing for particle identification in high-energy physics experiments S Balaji, D Meganathan Journal of Instrumentation 14 (07), C07013, 2019 | | 2019 |
| Radiation hardened high resolution timing generator S Balaji, S Ramasamy 2015 IEEE Asia Pacific Conference on Postgraduate Research in …, 2015 | | 2015 |
| Low jitter hybrid Phase Locked Loop RP Raj, S Balaji, KS Srinivasan, S Senthilnathan 2012 Third International Conference on Emerging Applications of Information …, 2012 | | 2012 |
| Facial Emotion Classification for Industry Automation using Convolutional Neural Networks RB Raam, B Srinivasan, P Rajalingam, DJ Samuel Industry Automation: The Technologies, Platforms and Use Cases, 237, 0 | | |
