Tong Li
Tong Li
Lenovo
Verified email at happyli.org - Homepage
Title
Cited by
Cited by
Year
Efficient operating system scheduling for performance-asymmetric multi-core architectures
T Li, D Baumberger, DA Koufaty, S Hahn
SC'07: Proceedings of the 2007 ACM/IEEE conference on Supercomputing, 1-11, 2007
3222007
Using OS observations to improve performance in multicore systems
R Knauerhase, P Brett, B Hohlt, T Li, S Hahn
IEEE micro 28 (3), 54-66, 2008
2852008
A large, fast instruction window for tolerating cache misses
AR Lebeck, J Koppanalil, T Li, J Patwardhan, E Rotenberg
ACM SIGARCH Computer Architecture News 30 (2), 59-70, 2002
2792002
Operating system support for overlapping-ISA heterogeneous multi-core architectures
T Li, P Brett, R Knauerhase, D Koufaty, D Reddy, S Hahn
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
1972010
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin
T Li, D Baumberger, S Hahn
ACM Sigplan Notices 44 (4), 65-74, 2009
1682009
Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution.
T Li, CS Ellis, AR Lebeck, DJ Sorin
USENIX Annual Technical Conference, General Track 44, 2005
782005
Soft real-time scheduling on performance asymmetric multicore platforms
JM Calandrino, D Baumberger, T Li, S Hahn, JH Anderson
13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS …, 2007
592007
Spin detection hardware for improved management of multithreaded systems
T Li, AR Lebeck, DJ Sorin
IEEE Transactions on Parallel and Distributed Systems 17 (6), 508-521, 2006
552006
LinSched: The Linux Scheduler Simulator.
JM Calandrino, DP Baumberger, T Li, JC Young, S Hahn
ISCA PDCCS, 171-176, 2008
462008
Two level re-order buffer
MJ Dechene, ST Srinivasan, MC Merten, T Li, CE Wang
US Patent 9,495,159, 2016
362016
Providing an asymmetric multicore processor system transparently to an operating system
B Ginzburg, I Osadchiy, R Ronen, E Weissmann, M Mishaeli, A Naveh, ...
US Patent 9,720,730, 2017
342017
Quantifying instruction criticality for shared memory multiprocessors
T Li, AR Lebeck, DJ Sorin
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and …, 2003
202003
Controlling access to a cache memory using privilege level information
Z Fang, L Zhao, R Iyer, T Li, DK Newell
US Patent 8,621,149, 2013
192013
Operating system support for shared-isa asymmetric multi-core architectures
T Li, P Brett, B Hohlt, R Knauerhase, SD McElderry, S Hahn
Workshop on the Interaction between Operating Systems and Computer …, 2008
192008
Thread migration control based on prediction of migration overhead
T Li, D Baumberger, S Hahn
US Patent 8,006,077, 2011
122011
My brain is full: When more memory helps
C Lusena, T Li, S Sittinger, C Wells, J Goldsmith
arXiv preprint arXiv:1301.6715, 2013
112013
Reducing L1 caches power by exploiting software semantics
Z Fang, L Zhao, X Jiang, S Lu, R Iyer, T Li, SE Lee
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
102012
Resource-aware application scheduling
J Moses, DK Newell, R Illikkal, R Iyer, S Makineni, L Zhao, S Hahn, TN Li, ...
US Patent App. 12/004,756, 2009
92009
Enhanced loop streaming detector to drive logic optimization
MC Merten, JM Deinlein, YN Ilin, AJ Farcy, T Li, ST Srinivasan
US Patent 9,354,875, 2016
82016
Addition instructions with independent carry chains
V Gopal, JD Guilford, GM Wolrich, WK Feghali, E Ozturk, MG Dixon, ...
US Patent App. 13/993,483, 2014
82014
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