| Part I: On the unification of physics of quasi-saturation in LDMOS devices BS Kumar, M Shrivastava IEEE Transactions on Electron Devices 65 (1), 191-198, 2017 | 29 | 2017 |
| Physics of current filamentation in ggNMOS devices under ESD condition revisited M Paul, C Russ, BS Kumar, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 65 (7), 2981-2989, 2018 | 17 | 2018 |
| Drain-extended FinFET with embedded SCR (DeFinFET-SCR) for high-voltage ESD protection and self-protected designs M Paul, BS Kumar, KK Nagothu, P Singhal, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 66 (12), 5072-5079, 2019 | 13 | 2019 |
| Physical insights into the low current ESD failure of LDMOS-SCR and its implication on power scalability NK Kranthi, BS Kumar, A Salman, G Boselli, M Shrivastava 2019 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2019 | 13 | 2019 |
| On the design challenges of drain extended FinFETs for advance SoC integration BS Kumar, M Paul, M Shrivastava 2017 International Conference on Simulation of Semiconductor Processes and …, 2017 | 13 | 2017 |
| Performance and reliability codesign for superjunction drain extended MOS devices J Somayaji, BS Kumar, MS Bhat, M Shrivastava IEEE Transactions on Electron Devices 64 (10), 4175-4183, 2017 | 11 | 2017 |
| Performance and reliability co-design of LDMOS-SCR for self-protected high voltage applications on-chip NK Kranthi, BS Kumar, A Salman, G Boselli, M Shrivastava 2019 31st International Symposium on Power Semiconductor Devices and ICs …, 2019 | 10 | 2019 |
| Performance and reliability insights of drain extended FinFET devices for high voltage SoC applications BS Kumar, M Paul, M Shrivastava, H Gossner 2018 IEEE 30th International Symposium on Power Semiconductor Devices and …, 2018 | 9 | 2018 |
| Part II: RF, ESD, HCI, SOA, and self heating concerns in LDMOS devices versus quasi-saturation BS Kumar, M Shrivastava IEEE Transactions on Electron Devices 65 (1), 199-206, 2017 | 9 | 2017 |
| FinFET SCR: Design challenges and novel fin SCR approaches for on-chip ESD protection M Paul, BS Kumar, C Russ, H Gossner, M Shrivastava 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 1-6, 2017 | 9 | 2017 |
| Challenges & physical insights into the design of fin-based SCRs and a novel fin-SCR for efficient on-chip ESD protection M Paul, BS Kumar, C Russ, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 65 (11), 4755-4763, 2018 | 7 | 2018 |
| Impact of space charge modulation on superjunction-LDMOS A Mishra, BS Kumar, J Somayaji, M Shrivastava, A Gupta 2020 International Symposium on VLSI Technology, Systems and Applications …, 2020 | 6 | 2020 |
| Physical insights into the ESD behavior of drain extended FinFETs (DeFinFETs) and unique current filament dynamics BS Kumar, M Paul, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 67 (7), 2717-2724, 2020 | 5 | 2020 |
| How to achieve moving current filament in high voltage LDMOS devices: Physical insights & design guidelines for self-protected concepts NK Kranthi, C Garg, BS Kumar, A Salman, G Boselli, M Shrivastava 2020 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2020 | 5 | 2020 |
| Physical insights into the ESD behavior of drain extended FinFETs BS Kumar, M Paul, H Gossner, M Shrivastava 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 1-7, 2018 | 5 | 2018 |
| Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications BS Kumar, M Paul, J Somayaji, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 67 (11), 4728-4735, 2020 | 4 | 2020 |
| Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability M Paul, BS Kumar, H Gossner, M Shrivastava 2018 IEEE International Reliability Physics Symposium (IRPS), 3E. 3-1-3E. 3-6, 2018 | 4 | 2018 |
| Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device P Milova, M Shrivastava, BS KUMAR, C Russ, H Gossner US Patent 10,629,586, 2020 | 3 | 2020 |
| Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability M Paul, BS Kumar, H Gossner, M Shrivastava IEEE Transactions on Electron Devices 67 (7), 2745-2751, 2020 | 2 | 2020 |
| Design insights to address low current ESD failure and power scalability issues in high voltage LDMOS-SCR devices NK Kranthi, BS Kumar, A Salman, G Boselli, M Shrivastava 2020 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2020 | 2 | 2020 |
Mayank ShrivastavaIndian Institute of Science BangaloreVerified email at iisc.ac.in
