| High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits A Anita Angeline, VS Kanchana Bhaaskaran ETRI Journal 41 (3), 383-395, 2019 | 18 | 2019 |
| Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit AA Angeline, VS Kanchana Bhaaskaran IET Circuits, Devices & Systems 13 (8), 1134-1141, 2019 | 17 | 2019 |
| Speed enhancement techniques for clock-delayed dual keeper domino logic style AA Angeline, VSK Bhaaskaran International Journal of Electronics 107 (8), 1239-1253, 2020 | 13 | 2020 |
| High performance domino logic circuit design by contention reduction A Anita Angeline, VS Kanchana Bhaaskaran VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 9 | 2018 |
| Design and implementation of single precision pipelined floating point co-processor M Sangwan, AA Angeline 2013 International Conference on Advanced Electronic Systems (ICAES), 79-82, 2013 | 9 | 2013 |
| Dynamic logic ALU design with reduced switching power RB Khaladkar, AA Angeline, VSK Bhaaskaran Indian Journal of Science and Technology 8 (20), 1-8, 2015 | 7 | 2015 |
| Design of a 16 bit RISC processor KV Rao, AA Angeline, VSK Bhaaskaran Indian Journal of Science and Technology 8 (20), 1, 2015 | 6 | 2015 |
| Design of Manchester Carry chain adder using high speed domino logic P Das, AL Bhalerao, A Mane, AA Angeline, VSK Bhaaskaran IOP Conference Series: Materials Science and Engineering 561 (1), 012125, 2019 | 4 | 2019 |
| ALU design using Pseudo Dynamic Buffer based domino logic SK Akurati, AA Angeline, VSK Bhaaskaran 2017 International Conference on Nextgen Electronic Technologies: Silicon to …, 2017 | 3 | 2017 |
| Design of process variation tolerant domino logic keeper architecture S Padhi, AA Angeline, VSK Bhaaskaran 2017 International Conference on Nextgen Electronic Technologies: Silicon to …, 2017 | 3 | 2017 |
| Dual threshold HSCD domino adder structures SA Vasant, AA Angeline, VSK Bhaaskaran 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 3 | 2016 |
| Design of variable width barrel shifter for RISC processor PV Priya, A Angeline International Journal of Research in Electronics & Communication Technology …, 2013 | 3 | 2013 |
| Domino logic keeper circuit design techniques: A review AA Angeline, VSK Bhaaskaran Journal of The Institution of Engineers (India): Series B, 1-11, 2021 | 2 | 2021 |
| TSPC based dynamic linear feedback shift register PP Ambalal, A Anita Angeline, VS Kanchana Bhaaskaran Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2016 | 2 | 2016 |
| Schmitt Trigger Designs Using Domino Logic Style N Singh, S Shekhar, A Angeline ECS Transactions 107 (1), 8885, 2022 | 1 | 2022 |
| Design and Implementation of Multi-bit Self-checking Carry Select Adder S Kavitkar, A Anita Angeline VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 1 | 2018 |
| Modified constant delay logic KV Rao, AA Angeline, VSK Bhaaskaran 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 1 | 2015 |
| Transmission Gate based Keeper Control for Domino Logic Circuits A Rout, S Dn, A Angeline, Sasipriya Proceedings of the 2022 Fourteenth International Conference on Contemporary …, 2022 | | 2022 |
| Low Power Memory System Design Using Power Gated SRAM Cell S Pal, DS Salimath, B Chandran, AA Angeline, VSK Bhaaskaran IOP Conference Series: Materials Science and Engineering 1187 (1), 012008, 2021 | | 2021 |
| High Performance Wallace Tree Multiplier Using Majority Gate Based Adders MM Murasu, S Sujith, AA Angeline, PS Priya, VSK Bhaaskaran IOP Conference Series: Materials Science and Engineering 1187 (1), 012003, 2021 | | 2021 |
V S Kanchana BhaaskaranPRO VICE CHANCELLOR, VIT CHENNAIVerified email at ieee.org
V S Kanchana BhaaskaranPRO VICE CHANCELLOR, VIT CHENNAIVerified email at ieee.org