| High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits A Anita Angeline, VS Kanchana Bhaaskaran ETRI Journal 41 (3), 383-395, 2019 | 19 | 2019 |
| Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit AA Angeline, VS Kanchana Bhaaskaran IET Circuits, Devices & Systems 13 (8), 1134-1141, 2019 | 18 | 2019 |
| Speed enhancement techniques for clock-delayed dual keeper domino logic style AA Angeline, VSK Bhaaskaran International Journal of Electronics 107 (8), 1239-1253, 2020 | 14 | 2020 |
| High performance domino logic circuit design by contention reduction A Anita Angeline, VS Kanchana Bhaaskaran VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 11 | 2018 |
| Design and implementation of single precision pipelined floating point co-processor M Sangwan, AA Angeline 2013 International Conference on Advanced Electronic Systems (ICAES), 79-82, 2013 | 9 | 2013 |
| Dynamic logic ALU design with reduced switching power RB Khaladkar, AA Angeline, VSK Bhaaskaran Indian Journal of Science and Technology, 2015 | 7 | 2015 |
| TSPC based dynamic linear feedback shift register PP Ambalal, A Anita Angeline, VS Kanchana Bhaaskaran Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2016 | 5 | 2016 |
| Design of Manchester Carry chain adder using high speed domino logic P Das, AL Bhalerao, A Mane, AA Angeline, VSK Bhaaskaran IOP Conference Series: Materials Science and Engineering 561 (1), 012125, 2019 | 4 | 2019 |
| ALU design using Pseudo Dynamic Buffer based domino logic SK Akurati, AA Angeline, VSK Bhaaskaran 2017 International Conference on Nextgen Electronic Technologies: Silicon to …, 2017 | 4 | 2017 |
| Domino logic keeper circuit design techniques: A review AA Angeline, VSK Bhaaskaran Journal of The Institution of Engineers (India): Series B, 1-11, 2021 | 3 | 2021 |
| Design of process variation tolerant domino logic keeper architecture S Padhi, AA Angeline, VSK Bhaaskaran 2017 International Conference on Nextgen Electronic Technologies: Silicon to …, 2017 | 3 | 2017 |
| Design of variable width barrel shifter for RISC processor PV Priya, A Angeline International Journal of Research in Electronics & Communication Technology …, 2013 | 3 | 2013 |
| Design of approximate restoring dividers for error resilient applications P Gowtham, P Sasipriya, AA Angeline ECS Transactions 107 (1), 13675, 2022 | 2 | 2022 |
| Schmitt trigger designs using domino logic style N Singh, S Shekhar, A Angeline ECS Transactions 107 (1), 8885, 2022 | 2 | 2022 |
| Dual threshold HSCD domino adder structures SA Vasant, AA Angeline, VSK Bhaaskaran 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 2 | 2016 |
| Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit AL Bhalerao, A Mane, K Pensenwar, BP Bhuvana, AA Angeline, ... Journal of Physics: Conference Series 1716 (1), 012033, 2020 | 1 | 2020 |
| Clock Delayed Dual Keeper Domino-Logic Design with Reduced Switching A Varghese, SR ANUSHA, AA Angeline, VSK BHAASKARAN International Journal of Engineering and Advanced Technology Special Issue 9 …, 2019 | 1 | 2019 |
| Design and Implementation of Multi-bit Self-checking Carry Select Adder S Kavitkar, A Anita Angeline VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 1 | 2018 |
| Modified constant delay logic KV Rao, AA Angeline, VSK Bhaaskaran 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 1 | 2015 |
| Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications V Gundavarapu, P Gowtham, AA Angeline, P Sasipriya Microprocessors and Microsystems 106, 105036, 2024 | | 2024 |
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org