| TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture—part I: hot-carrier-reliability evaluation R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta IEEE transactions on electron devices 55 (10), 2602-2613, 2008 | 41 | 2008 |
| Marketing strategies 4.0: recent trends and technologies in marketing R Kaur, R Singh, A Gehlot, N Priyadarshi, B Twala Sustainability 14 (24), 16356, 2022 | 33 | 2022 |
| Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Superlattices and Microstructures 44 (2), 143-152, 2008 | 32 | 2008 |
| Laterally amalgamated DUal material GAte concave (L-DUMGAC) MOSFET for ULSI R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Microelectronic engineering 85 (3), 566-576, 2008 | 26 | 2008 |
| TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal … R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Superlattices and Microstructures 46 (4), 645-655, 2009 | 21 | 2009 |
| Two-dimensional analytical model to characterize novel MOSFET architecture: Insulated shallow extension MOSFET R Kaur, R Chaujar, M Saxena, RS Gupta semiconductor Science and Technology 22 (8), 952, 2007 | 19 | 2007 |
| Modeling and analysis of fully strained and partially relaxed lattice mismatched AlGaN/GaN HEMT for high temperature applications P Gangwani, R Kaur, S Pandey, S Haldar, M Gupta, RS Gupta Superlattices and Microstructures 44 (6), 781-793, 2008 | 18 | 2008 |
| Hot-carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET R Kaur, R Chaujar, M Saxena, RS Gupta IEEE transactions on electron devices 54 (9), 2556-2561, 2007 | 15 | 2007 |
| Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration R Kaur, R Chaujar, M Saxena, RS Gupta Microelectronic engineering 86 (10), 2005-2014, 2009 | 8 | 2009 |
| Performance investigation of 50-nm insulated-shallow-extension gate-stack (ISEGaS) MOSFET for mixed mode applications R Kaur, R Chaujar, M Saxena, RS Gupta IEEE transactions on electron devices 54 (2), 365-368, 2007 | 8 | 2007 |
| Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta International Journal of Numerical Modelling: Electronic Networks, Devices …, 2009 | 7 | 2009 |
| Unified subthreshold model for channel-engineered sub-100-nm advanced MOSFET structures R Kaur, R Chaujar, M Saxena, RS Gupta IEEE transactions on electron devices 54 (9), 2475-2486, 2007 | 7 | 2007 |
| A smart learning assistance tool for inclusive education S Srivastava, A Varshney, S Katyal, R Kaur, V Gaur Journal of Intelligent & Fuzzy Systems 40 (6), 11981-11994, 2021 | 6 | 2021 |
| Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance R Kaur, R Chaujar, M Saxena, RS Gupta Microwave and Optical Technology Letters 52 (3), 770-775, 2010 | 6 | 2010 |
| T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable … R Gupta, S Rathi, R Kaur, M Gupta, RS Gupta Superlattices and Microstructures 45 (3), 105-116, 2009 | 6 | 2009 |
| On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Semiconductor science and technology 23 (9), 095009, 2008 | 6 | 2008 |
| Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Semiconductor science and technology 23 (4), 045006, 2008 | 6 | 2008 |
| Stereoselective Reductive Coupling Reactions Utilizing [1, 2]-Phospha-Brook Rearrangement: A Powerful Umpolung Approach R Kaur, RP Singh The Journal of Organic Chemistry 88 (15), 10325-10338, 2023 | 5 | 2023 |
| Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta Semiconductor science and technology 24 (6), 065005, 2009 | 5 | 2009 |
| Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta 2008 2nd National Workshop on Advanced Optoelectronic Materials and Devices …, 2008 | 5 | 2008 |
Prof. Rishu ChaujarDepartment of Applied Physics, Delhi Technological UniversityVerified email at dtu.ac.in
