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Amol Gaidhane
Amol Gaidhane
Postdoctoral Researcher, Arizona State University || Ph.D., IIT Kanpur
Verified email at asu.edu
Title
Cited by
Cited by
Year
Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance
H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan
IEEE Access 6, 52754-52765, 2018
782018
Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
IEEE Transactions on Electron Devices 65 (5), 2024-2032, 2018
682018
Impact of variability on processor performance in negative capacitance finfet technology
H Amrouch, G Pahwa, AD Gaidhane, CK Dabhi, F Klemme, O Prakash, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3127-3137, 2020
552020
Unveiling the impact of IR-drop on performance gain in NCFET-based processors
H Amrouch, S Salamin, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan
IEEE Transactions on Electron Devices 66 (7), 3215-3223, 2019
292019
Gate-induced drain leakage in negative capacitance FinFETs
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
IEEE Transactions on Electron Devices 67 (3), 802-809, 2020
222020
A computationally efficient compact model for ferroelectric switching with asymmetric non-periodic input signals
AD Gaidhane, R Dangi, S Sahay, A Verma, YS Chauhan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
142022
Compact modeling of surface potential, drain current and terminal charges in negative capacitance nanosheet FET including quasi-ballistic transport
AD Gaidhane, G Pahwa, A Dasgupta, A Verma, YS Chauhan
IEEE Journal of the Electron Devices Society 8, 1168-1176, 2020
142020
Ferroelectric fdsoi fet modeling for memory and logic applications
S Chatterjee, S Kumar, A Gaidhane, CK Dabhi, YS Chauhan, H Amrouch
Solid-State Electronics 200, 108554, 2023
112023
Ferroelectric FET-based implementation of Fitzhugh-Nagumo neuron model
D Rajasekharan, A Gaidhane, AR Trivedi, YS Chauhan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
112021
Compact modeling of drain current in double gate negative capacitance MFIS transistor
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
2018 4th IEEE International Conference on Emerging Electronics (ICEE), 1-5, 2018
102018
Modeling of inner fringing charges and short channel effects in negative capacitance MFIS transistor
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 282-284, 2019
92019
Modeling of multi-domain switching in ferroelectric materials: Application to negative capacitance FETs
A Dasgupta, P Rastogi, D Saha, A Gaidhane, A Agarwal, YS Chauhan
2018 IEEE International Electron Devices Meeting (IEDM), 9.2. 1-9.2. 4, 2018
82018
Assessing negative-capacitance drain-extended technology for high-voltage switching and analog applications
G Pahwa, AD Gaidhane, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 68 (2), 679-687, 2020
72020
Study of multi-domain switching dynamics in negative capacitance FET using SPICE model
AD Gaidhane, A Verma, YS Chauhan
Microelectronics Journal 115, 105186, 2021
62021
A computationally efficient compact model for ferroelectric FinFETs switching with asymmetric non-periodic input signals
S Sahay, A Gaidhane, YS Chauhan, R Dangi, A Verma
Authorea Preprints, 2023
52023
Compact modeling of negative capacitance nanosheet FET including quasi-ballistic transport
AD Gaidhane, G Pahwa, A Dasgupta, A Verma, YS Chauhan
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020
42020
Design Exploration of 14nm FinFET for Energy Efficient Cryogenic Computing
AD Gaidhane, R Saligram, W Chakraborty, S Datta, A Raychowdhury, ...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023
22023
Graph-Based Compact Model (GCM) for Efficient Transistor Parameter Extraction: A Machine Learning Approach on 12 nm FinFETs
Z Yang, AD Gaidhane, K Anderson, G Workman, Y Cao
IEEE Transactions on Electron Devices, 2023
22023
Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach
AD Gaidhane, Z Yang, Y Cao
Solid-State Electronics 201, 108580, 2023
22023
Physics-constrained graph modeling for building thermal dynamics
Z Yang, AD Gaidhane, J Drgoňa, V Chandan, MM Halappanavar, F Liu, ...
Energy and AI 16, 100346, 2024
12024
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