| Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor N Kannan, MJ Kumar Electron Device Letters, IEEE 34 (12), 1575 - 1577, 2013 | 125 | 2013 |
| Charge-Modulated Underlap I-MOS Transistor as a Label-Free Biosensor: A Simulation Study N Kannan, MJ Kumar IEEE Transactions on Electron Devices 62 (8), 2645-2651, 2015 | 43 | 2015 |
| Capacitive cell load estimation using electromigration analysis P Sharma, M Kashyap, N Kannan US Patent 8,843,873, 2014 | 5 | 2014 |
| Schottky bipolar I-MOS: An I-MOS with Schottky electrodes and an open-base BJT configuration for reduced operating voltage N Kannan, MJ Kumar Superlattices and Microstructures 104, 422-427, 2017 | 3 | 2017 |
| A Drain-side Gate-underlap I-MOS (DGI-MOS) transistor as a label-free biosensor for detection of charged biomolecules N Kannan, MJ Kumar 2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-4, 2014 | 3 | 2014 |
| Thin capacitively-coupled thyristor as an ultrasensitive label-free nanogap biosensor: Proposal and investigation N Kannan, S Kalra, MJ Kumar IEEE sensors letters 1 (6), 1-4, 2017 | 2 | 2017 |
| System for placing dummy tiles in metal layers of integrated circuit design A Jain, N Kannan US Patent 8,898,612, 2014 | 2 | 2014 |
| A semiconductor bio sensing device for detecting biological compound contained in an electrolyte MJ KUMAR, N KALRA, Sumeet and KANNAN IN Patent 476,966, 2017 | | 2017 |
| Optimizing SoC Implementation Cycle with Continuous Verification and Signoff Using PVS VK Ankit Jain, N Kannan, Jonathan Lee Cadence Technology Forum 2017, 2017 | | 2017 |
| System and method for clocking integrated circuit N Kannan, R Srivastava US Patent 9,438,217, 2016 | | 2016 |
| Analyzing Digital Self Heating Effect and its impact on EM using Voltus - 2016 SK Paul Mathew, N Kannan CDNLive India, 2016 | | 2016 |
| Handling Power and IR drop challenges in sub-micron technologies using Voltus NK Sachin Kalra, Vijay Tayal, Amit Dey, Paul Mathew CDNLive India, 2015, 2015 | | 2015 |
| An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect BK Dalai, N Karnnan, A Sharma, B Anand 18th International Symposium on VLSI Design and Test, 1-2, 2014 | | 2014 |
| A Method for Efficient Core Power-Up Analysis in Multi-Core SoC Designs GK N Kannan, Shivraj Byru 51st Design Automation Conference, 2014 | | 2014 |
| Schematic Based Generation of Power Internt Specification (CPF) for Analog IPs AC N Kannan, Sandeep Jasrotia, Sorabh Sachdeva, Nitin Bhardwaj 27th International Conference on VLSI Design, 2014 | | 2014 |
| Method and Apparatus for non-simulation based estimation of input pin capacitance of hard IPs SA N Kannan 50th Design Automation Conference, Designer Track, 2013 | | 2013 |
| Power, Noise and Reliability Considerations for Advanced Automotive and Networking ICs N Kannan 50th Design Automation Conference - ANSYS-Apache Customer Presentation, 2013 | | 2013 |
| Method and Apparatus for Design-Agnostic Power Network Integrity check for hard IPs GK N Kannan IP.com Disclosure Number: IPCOM000225355D, 2013 | | 2013 |
| Impact of Package and On-Die Power Distribution Network on the relative performance of individual Cores in a multi-Core SoC GK N Kannan 26th International Conference on VLSI Design, 2013 | | 2013 |
| Method and Apparatus for Non-simulation Based Estimation of Input Pin Capacitance of Hard IPs SA N Kannan http://priorart.ip.com/IPCOM/000222850, 2012 | | 2012 |
Mamidala Jagadesh Kumar.Indian Institute of Technology Delhi; Chairman, UGCVerified email at ee.iitd.ac.in
