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Ioannis Tsiokanos
Ioannis Tsiokanos
Verified email at qub.ac.uk
Title
Cited by
Cited by
Year
Low-power variation-aware cores based on dynamic data-dependent bitwidth truncation
I Tsiokanos, L Mukhanov, G Karakonstantis
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 698-703, 2019
232019
Accurate estimation of dynamic timing slacks using event-driven simulation
D Garyfallou, I Tsiokanos, N Evmorfopoulos, G Stamoulis, ...
2020 21st International Symposium on Quality Electronic Design (ISQED), 225-230, 2020
172020
Defcon: Generating and detecting failure-prone instruction sequences via stochastic search
I Tsiokanos, L Mukhanov, G Georgakoudis, DS Nikolopoulos, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
112020
DTA-PUF: Dynamic timing-aware physical unclonable function for resource-constrained devices
I Tsiokanos, J Miskelly, C Gu, M O’neill, G Karakonstantis
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-24, 2021
102021
Significance-driven data truncation for preventing timing failures
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
IEEE Transactions on Device and Materials Reliability 19 (1), 25-36, 2019
102019
Variation-aware pipelined cores through path shaping and dynamic cycle adjustment: Case study on a floating-point unit
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
Proceedings of the International Symposium on Low Power Electronics and …, 2018
102018
Boosting microprocessor efficiency: Circuit-and workload-aware assessment of timing errors
I Tsiokanos, G Papadimitriou, D Gizopoulos, G Karakonstantis
2021 IEEE International Symposium on Workload Characterization (IISWC), 125-137, 2021
82021
Estimating code vulnerability to timing errors via microarchitecture-aware machine learning
S Tompazi, I Tsiokanos, JM del Rincon, G Karakonstantis
IEEE Design & Test 40 (1), 34-42, 2021
62021
ExHero: Execution history-aware error-rate estimation in pipelined designs
I Tsiokanos, G Karakonstantis
IEEE Micro 41 (1), 61-68, 2020
62020
Minimization of timing failures in pipelined designs via path shaping and operand truncation
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018
52018
Instruction-aware learning-based timing error models through significance-driven approximations
S Tompazi, I Tsiokanos, JM del-Rincon, L Mukhanov, G Karakonstantis
2022 IEEE 40th International Conference on Computer Design (ICCD), 455-462, 2022
32022
Arete: Accurate error assessment via machine learning-guided dynamic-timing analysis
I Tsiokanos, S Tompazi, G Georgakoudis, L Mukhanov, G Karakonstantis
IEEE Transactions on Computers 72 (4), 1026-1040, 2022
32022
Hardware Level Approximations
I Tsiokanos, G Papadimitriou, D Gizopoulos, G Karakonstantis
Approximate Computing Techniques: From Component-to Application-Level, 43-79, 2022
2022
Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
I Tsiokanos
Queen's University Belfast, 2021
2021
SPECIAL SECTION ON IOLTS
D Gizopoulos, D Alexandrescu, M Nicolaidis, LB Faber, ML Flottes, ...
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