Transistors based on two-dimensional materials for future integrated circuits S Das, A Sebastian, E Pop, CJ McClellan, AD Franklin, T Grasser, ... Nature Electronics 4 (11), 786-799, 2021 | 604 | 2021 |
Tunnel field-effect transistors: Prospects and challenges UE Avci, DH Morris, IA Young IEEE Journal of the Electron Devices Society 3 (3), 88-95, 2015 | 528 | 2015 |
Scaled TFET transistor formed using nanowire with surface termination UE Avci, R Rios, KJ Kuhn, IA Young, JR Weber US Patent 10,535,770, 2020 | 390 | 2020 |
Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic UE Avci, R Rios, K Kuhn, IA Young 2011 Symposium on VLSI Technology-Digest of Technical Papers, 124-125, 2011 | 166 | 2011 |
Three-dimensional ferroelectric NOR-type memory DH Morris, UE Avci, IA Young US Patent 10,651,182, 2020 | 165 | 2020 |
Floating body cell with independently-controlled double gates for high density memory I Ban, UE Avci, U Shah, CE Barns, DL Kencke, P Chang 2006 International Electron Devices Meeting, 1-4, 2006 | 135 | 2006 |
Floating body memory cell having gates favoring different conductivity type regions PLD Chang, UE Avci, DL Kencke, I Ban US Patent 8,217,435, 2012 | 128 | 2012 |
Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors R Kotlyar, UE Avci, S Cea, R Rios, TD Linton, KJ Kuhn, IA Young Applied Physics Letters 102 (11), 2013 | 119 | 2013 |
Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length UE Avci, IA Young 2013 IEEE International Electron Devices Meeting, 4.3. 1-4.3. 4, 2013 | 118 | 2013 |
Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics DH Morris, UE Avci, R Rios, IA Young IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014 | 108 | 2014 |
The ultimate CMOS device and beyond KJ Kuhn, U Avci, A Cappellani, MD Giles, M Haverty, S Kim, R Kotlyar, ... 2012 International Electron Devices Meeting, 8.1. 1-8.1. 4, 2012 | 96 | 2012 |
Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations UE Avci, DH Morris, S Hasan, R Kotlyar, R Kim, R Rios, DE Nikonov, ... 2013 IEEE International Electron Devices Meeting, 33.4. 1-33.4. 4, 2013 | 92 | 2013 |
Physical origin of transient negative capacitance in a ferroelectric capacitor SC Chang, UE Avci, DE Nikonov, S Manipatruni, IA Young Physical Review Applied 9 (1), 014010, 2018 | 90 | 2018 |
Advancing 2D monolayer CMOS through contact, channel and interface engineering KP O'Brien, CJ Dorow, A Penumatcha, K Maxey, S Lee, CH Naylor, ... 2021 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2021 | 88 | 2021 |
Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results UE Avci, S Hasan, DE Nikonov, R Rios, K Kuhn, IA Young 2012 Symposium on VLSI Technology (VLSIT), 183-184, 2012 | 73 | 2012 |
3d-ferroelectric random access memory (3d-fram) S Shivaraman, SC Chang, AV Penumatcha, N Haratipour, UE Avci US Patent App. 16/599,422, 2021 | 67 | 2021 |
Asymmetric Metal/α-In2Se3/Si Crossbar Ferroelectric Semiconductor Junction M Si, Z Zhang, SC Chang, N Haratipour, D Zheng, J Li, UE Avci, PD Ye ACS nano 15 (3), 5689-5695, 2021 | 65 | 2021 |
Advancing monolayer 2-D nMOS and pMOS transistor integration from growth to van der Waals interface engineering for ultimate CMOS scaling C Dorow, K O’Brien, CH Naylor, S Lee, A Penumatcha, A Hsiao, T Tronic, ... IEEE Transactions on Electron Devices 68 (12), 6592-6598, 2021 | 63 | 2021 |
Field Effect Transistors Having Ferroelectric or Antiferroelectric Gate Dielectric Structure S Kim, UE Avci, JM Howard, IA Young, DH Morris US Patent 11,735,652, 2023 | 58 | 2023 |
Roadmap on ferroelectric hafnia-and zirconia-based materials and devices JPB Silva, R Alcala, UE Avci, N Barrett, L Bégon-Lours, M Borg, S Byun, ... APL Materials 11 (8), 2023 | 56 | 2023 |