Dr. Shiromani Balmukund  Rahi
Dr. Shiromani Balmukund Rahi
Assistant Professor(Gautam Buddha University)&Associated-Researcher|(IIT Kanpur),|Editor|,|Reviewer|
Verified email at - Homepage
Cited by
Cited by
Heterogate junctionless tunnel field-effect transistor: future of low-power devices
SB Rahi, P Asthana, S Gupta
Journal of Computational Electronics 16, 30-38, 2017
A review on emerging negative capacitance field effect transistor for low power electronics
SB Rahi, S Tayal, AK Upadhyay
Microelectronics Journal 116, 105242, 2021
Temperature effect on hetero structure junctionless tunnel FET
SB Rahi, B Ghosh, B Bishnoi
Journal of semiconductors 36 (3), 034002, 2015
Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications
PK Asthana, Y Goswami, S Basak, SB Rahi, B Ghosh
RSC Advances 5 (60), 48779-48785, 2015
High-k double gate junctionless tunnel FET with a tunable bandgap
SB Rahi, B Ghosh
RSC Advances 5 (67), 54544-54550, 2015
Optimal design for a high performance H-JLTFET using HfO 2 as a gate dielectric for ultra low power applications
PK Asthana, B Ghosh, SBM Rahi, Y Goswami
RSC Advances 4 (43), 22803-22807, 2014
Identifying the moderating effect of trust on the adoption of cloud‐based services
SB Rahi, S Bisui, SC Misra
International Journal of Communication Systems 30 (11), e3253, 2017
Recent progress on negative capacitance tunnel FET for low-power applications: Device perspective
AK Upadhyay, SB Rahi, S Tayal, YS Song
Microelectronics Journal 129, 105583, 2022
A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET
SB Rahi, B Ghosh, P Asthana
Journal of semiconductors 35 (11), 114005, 2014
Identifying critical challenges in the adoption of cloud‐based services
SB Rahi, S Bisui, SC Misra
International Journal of Communication Systems 30 (12), e3261, 2017
Rigorous study of double gate tunneling field effect transistor structure based on silicon
N Guenifi, SB Rahi, T Ghodbane
Materials Focus 7 (6), 866-872, 2018
Incorporating bottom-up approach into device/circuit co-design for SRAM-based cache memory applications
S Tayal, B Smaani, SB Rahi, AK Upadhyay, S Bhattacharya, J Ajayan, ...
IEEE Transactions on Electron Devices 69 (11), 6127-6132, 2022
Suppression of Ambipolar Current and Analysis of RF Performance in Double Gate Tunneling Field Effect Transistors for Low-Power Applications
SBRML N Guenifi
International Journal of Nanoparticles and Nanotechnology 6 (1), 1-12, 2020
Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET
M Sathishkumar, TSA Samuel, K Ramkumar, IV Anand, SB Rahi
Superlattices and Microstructures 162, 107099, 2022
Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect
S Gupta, B Ghosh, SB Rahi
Journal of Semiconductors 36 (2), 024001, 2015
Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell
D Kumar
Engineering Research Express 1 (2), 025055, 2019
Factors influencing the success of cloud adoption in the semiconductor industry
SC Misra, SB Rahi, S Bisui, A Singh
Software Quality Professional 21 (2), 38-51, 2019
Emerging low-power semiconductor devices: Applications for future technology nodes
S Tayal, AK Upadhyay, D Kumar, SB Rahi
CRC Press, 2022
Electrical and Electronic Devices, Circuits, and Materials: Technological Challenges and Solutions
SL Tripathi, PA Alvi, U Subramaniam
John Wiley & Sons, 2021
Low power circuit and system design hierarchy and thermal reliability of tunnel field effect transistor
G Naima, SB Rahi
Silicon, 1-11, 2021
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