0.84 ps resolution clock skew measurement via subsampling B Amrutur, PK Das, R Vasudevamurthy IEEE transactions on very large scale integration (VLSI) systems 19 (12 …, 2010 | 23 | 2010 |
Time-Based All-Digital Technique for Analog Built-in Self-Test R Vasudevamurthy, PK Das, B Amrutur Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22 (2 …, 2014 | 12 | 2014 |
On-chip clock network skew measurement using sub-sampling PK Das, B Amrutur, J Sridhar, V Visvanathan 2008 IEEE Asian Solid-State Circuits Conference, 401-404, 2008 | 11 | 2008 |
An accurate fractional period delay generation system PK Das, B Amrutur IEEE Transactions on Instrumentation and Measurement 61 (7), 1924-1932, 2012 | 9 | 2012 |
A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test R Vasudevamurthy, PK Das, B Amrutur 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2035-2038, 2011 | 9 | 2011 |
A SYSTEM TO GENERATE A PREDETERMINED FRACTIONAL PERIOD TIME DELAY B AMRUTUR, PK DAS IN Patent App. 4212/CHE/2,012, 2016 | 5 | 2016 |
System to generate a Predetermined Fractional Period Time Delay B Amrutur, PK Das US Patent 8,664,994, 2014 | 5 | 2014 |
Methods and systems for measuring and reducing clock skew using a clock distribution network B Amrutur, PK Das US Patent 8,443,330, 2013 | | 2013 |
Design and fabrication of scan tube for field measurement of superconducting magnet of ion trap project at VECC S Saha, M Ahammed, S Singh, B Hemram, YE Rao, NP Mandai, ... Indian Cryogenics Council 37 (1to4), 99-103, 2012 | | 2012 |
Design of FF with low setup and hold times across process variations PK Das, B Amrutur, J Sridhar | | 2007 |
National demonstration on composite fish culture in West Bengal [India] P Das, D Kumar, MKG Roy Journal of the Inland Fisheries Society of India (India) 7, 1976 | | 1976 |
DESIGN OF FLIP-FLOPS WITH LOW SETUP AND HOLD TIMES ACROSS PROCESS VARIATIONS PK Das, B Amrutur, J Sridhar | | |