| Extended- Stepped Gate LDMOS for Improved Performance MJ Kumar, R Sithanandam IEEE Transactions on Electron Devices 57 (7), 1719-1724, 2010 | 90 | 2010 |
| Linearity and speed optimization in SOI LDMOS using gate engineering R Sithanandam, MJ Kumar Semiconductor science and technology 25 (1), 015006, 2009 | 28 | 2009 |
| ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process A Dray, N Guitard, P Fonteneau, D Golanski, C Fenouillet-Beranger, ... Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, 1-7, 2012 | 20 | 2012 |
| Electrostatic discharge (ESD) protection circuits using tunneling field effect transistor (TFET) and impact ionization MOSFET (IMOS) devices R Sithanandam US Patent 10,998,721, 2021 | 15 | 2021 |
| A novel cascade-free 5-V ESD clamp using I-MOS: Proposal and analysis R Sithanandam, MJ Kumar IEEE Transactions on Device and Materials Reliability 16 (2), 200-207, 2016 | 14 | 2016 |
| A new hetero-material stepped gate (HSG) SOI LDMOS for RF power amplifier applications R Sithanandam, MJ Kumar 2010 23rd International Conference on VLSI Design, 230-234, 2010 | 14 | 2010 |
| A new on-chip ESD strategy using TFETs-TCAD based device and network simulations R Sithanandam, MJ Kumar IEEE Journal of the Electron Devices Society 6, 298-308, 2018 | 13 | 2018 |
| Full swing positive to negative MOSFET supply clamp for electrostatic discharge (ESD) protection D Agarwal, R Sithanandam US Patent 11,081,881, 2021 | 11 | 2021 |
| Power supply clamp for electrostatic discharge (ESD) protection having a circuit for controlling clamp time out behavior V Batra, R Sithanandam US Patent 10,811,873, 2020 | 9 | 2020 |
| Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection R Sithanandam, D Agarwal, G Troussier, J Jimenez, M Kar US Patent 11,063,429, 2021 | 7 | 2021 |
| Extended-p+ stepped gate LDMOS for improved performance M Jagadesh Kumar, R Sithanandam IEEE transactions on electron devices 57 (7), 1719-1724, 2010 | 4 | 2010 |
| A new SiGe stepped gate (SSG) thin film SOI LDMOS for enhanced breakdown voltage and reduced delay R Sithanandam, MJ Kumar Proc. ISDRS, 1-2, 2009 | 4 | 2009 |
| Technology Scaling of ESD Devices in State of the Art FinFET Technologies S Kim, R Sithanandam, W Seo, M Lee, S Cho, J Park, H Kwon, N Kim, ... 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-6, 2020 | 1 | 2020 |
| Unexpected Latchup Risk Observed in FDSOI Technology–Analysis and Prevention Techniques R Sithanandam, C Jeon, K Lee, W Seo, K Song, Y Kim, J Davis, S Kim, ... 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 1-7, 2018 | 1 | 2018 |
| Analytical modeling of sub-onset current of tunnel field effect transistor P Singh, V Asthana, R Sithanandam, A Bulusu, SD Gupta 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 1 | 2014 |
| Design of SOI LDMOS for Base station and Wireless SOC Applications R Sithanandam LAP LAMBERT Academic Publishing, 2012 | 1 | 2012 |
| Electrostatic discharge (esd) protection circuits using tunneling field effect transistor (tfet) and impact ionization mosfet (imos) devices R Sithanandam US Patent App. 18/207,493, 2023 | | 2023 |
| Electrostatic discharge (ESD) protection circuits using tunneling field effect transistor (TFET) and impact ionization MOSFET (IMOS) devices R Sithanandam US Patent 11,710,961, 2023 | | 2023 |
| Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection R Sithanandam, D Agarwal, G Troussier, J Jimenez, M Kar US Patent 11,658,479, 2023 | | 2023 |
| Integrated silicon controlled rectifier (SCR) and a low leakage SCR supply clamp for electrostatic discharge (ESP) protection R Sithanandam, D Agarwal, J Jimenez, M Kar US Patent 10,944,257, 2021 | | 2021 |
