SEGR hardened superjunction VDMOS with high-K gate dielectrics S Ranjan, S Majumder, A Naugarhiya 2020 International Conference on Power Electronics & IoT Applications in …, 2020 | 9 | 2020 |
Analysis of Single Event Gate Rupture in Trench Gate SJ-VDMOS with SiO2-Si3N4 Dielectric Stacking R Verma, S Ranjan, A Naugarhiya 2021 IEEE Region 10 Symposium (TENSYMP), 1-6, 2021 | 6 | 2021 |
SEGR Analysis of Super Junction VDMOS using HfO2 as Gate Dielectric M Amjath, S Ranjan, A Naugarhiya 2022 Second International Conference on Advances in Electrical, Computing …, 2022 | 5 | 2022 |
Analysis of Gate Oxides in LDMOS for Radiation Hardening Against SEGR J Pavuluri, SM Ranjan, A Naugarhiya 2022 International Conference on Intelligent Controller and Computing for …, 2022 | | 2022 |
A Low Power 10 Bit 40 Msps Pipelined ADC VN Sanjeev M. Ranjan, Ritesh Bohra IEEE Xplore Digital Library 1295, 2012 | | 2012 |
A Low power, 10-PS Dead Zone Phase Frequency Detector in 0.18um CMOS Technology for Phase Locked Loop System SSL S. M. Ranjan, R.H Talwekar WASET World Academy of Science Engineering and Technology, Singapore, 868-871, 2010 | | 2010 |
Highly programmable/Tunable cross coupled operational transconductance amplifier with high tunning range JRV S. M. Ranjan, R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade first international conference on “Frontier Technologies-Need for the …, 2006 | | 2006 |
Design and implementation of low-cost power-optimized OTA-based FPAA in 0.35um MM CMOS process RDK P. Gawande, M. Chhangani, J. Verma, M. Patil, S. M. Ranjan N. Ingole, M ... Proc. of CDNLive 2006, 2006 | | 2006 |
Design of FPAA using custom IC and optimization-based design flow PG 1. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M. V ... Proc. of CDNLive USA, 2006 | | 2006 |
Design of low power FPAA in 0.35u CMOS Process NKIPG 1. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M ... IASTED ICCSS USA, 2006 | | 2006 |