Ramesh S R
Ramesh S R
Assistant Professor(Senior Grade), ECE Department Amrita Vishwa Vidyapeetham Coimbatore
Verified email at cb.amrita.edu
TitleCited byYear
A Survey of SSTA Techniques with Focus on Accuracy and Speed
SRR Bhaghath P J
International Journal of Computer Applications 89 (7), 21-25, 2014
62014
Toggle rate estimation technique for FPGA circuits considering spatial correlation
PJ Anju, SR Ramesh
2012 Third International Conference on Computing, Communication and …, 2012
52012
Improved Statistical Static Timing Analysis Using Refactored Timing Graphs
JR Ramesh SR
Journal of Computational and Theoretical NanoScience 13 (11), 8879-8884, 2016
42016
Design and Implementation of an Optimized Double Precision Floating Point Divider on FPGA
SR Ramesh
International Journal of Advanced Science and Technology 18, 41-48, 2010
42010
Probabilistic Activity Estimator and Timing Analysis for LUT Based Circuits
RJ Ramesh.S.R
International Journal Of Applied Engineering Research 10 (13), 33238-33242, 2015
32015
Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits
K Manikanth, SR Ramesh
2018 International Conference on Communication and Signal Processing (ICCSP …, 2018
22018
A comparison on timing analysis using probabilistic approaches
PJ Bhaghath, SR Ramesh
2014 International Conference on Communication and Signal Processing, 547-551, 2014
22014
An Efficient Booth Multiplier Using Probabilistic Approach
MVD Pavan, SR Ramesh
2018 International Conference on Communication and Signal Processing (ICCSP …, 2018
12018
Statistical Viability Analysis and Optimization Through Gate Sizing
K Sreenath, SR Ramesh
Advanced Computational and Communication Paradigms, 149-155, 2018
12018
Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers
H Haritha, SR Ramesh
2017 14th IEEE India Council International Conference (INDICON), 1-5, 2017
12017
Toggle Rate Estimation Technique for 4-Input LUT based FPGA Circuits
APJ Ramesh S R
International Journal of Engineering Research and Applications 2 (3), 198-203, 2012
1*2012
An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics
ASK Vamsi, SR Ramesh
2019 International Conference on Communication and Signal Processing (ICCSP …, 2019
2019
Design of Millimeter Wave LC Oscillators for 5G Applications
S Ramesh, M Nithin, HM Kittur
2019 International Conference on Communication and Signal Processing (ICCSP …, 2019
2019
A Low Power Binary Square rooter using Reversible Logic
A Krishna, G Priyadarsini, S Raghul, SR Ramesh
2019 5th International Conference on Advanced Computing & Communication …, 2019
2019
Design of Delay Efficient Hybrid Adder for High Speed Applications
J Nithya, SR Ramesh
2019 5th International Conference on Advanced Computing & Communication …, 2019
2019
VLSI implementation of LNS arithmetic unit by LUT partitioning
V Vinod, K Eswar, P Vishnuvardhan, G Srikanth, SR Ramesh
2017 International Conference on Advances in Computing, Communications and …, 2017
2017
Toggle rate estimation and glitch analysis on logic circuits
SR Ramesh, R Jayaparvathy
2017 IEEE International Workshop On Integrated Power Packaging (IWIPP), 1-5, 2017
2017
Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density
RSR PremLal Paleri
International Journal Of Applied Engineering Research 10 (11), 28889-28902, 2015
2015
An Efficient FIR Filter Design using CSE Method
ND Ramesh.S.R,Sai priya.V,N.Swetha Reddy,V.M.Abitha Mogi,K.S.Sakthi Keerthana
International Conference on Intelligent Engineering Systems, 2014
2014
Design of an Area Optimized Double Precision Floating Point Divider on FPGA
SK Ramesh S R
First International Conference on Intelligent Information Systems …, 2012
2012
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