| Arbiter PUF-a review of design, composition, and security aspects S Hemavathy, VSK Bhaaskaran IEEE Access, 2023 | 15 | 2023 |
| Double edge-triggered tristate flip-flop physical unclonable function for secure IoT ecosystem S Hemavathy, VSK Bhaaskaran 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 44-47, 2021 | 5 | 2021 |
| Design and analysis of secure quasi-adiabatic tristate physical unclonable function S Hemavathy, VSK Bhaaskaran 2020 IEEE International symposium on smart electronic systems (iSES …, 2020 | 5 | 2020 |
| Design of Vedic multiplier using reversible logic gates A Awade, P Jain, S Hemavathy, VS Kanchana Bhaaskaran Advances in Electrical and Computer Technologies: Select Proceedings of …, 2021 | 1 | 2021 |
| Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function HSVSK Bhaaskaran IEEE Consumer Electronics Magazine 11 (4), 98-104, 2022 | | 2022 |
| TEL Based Pre-Scaler Design S Pal, DS Salimath, K Sarkar, S Hemavathy, VSK Bhaaskaran 2022 IEEE Delhi Section Conference (DELCON), 1-5, 2022 | | 2022 |
| Secret Key Generation: Single Edge-Triggered Flip-Flop PUF for IoT Environment S Hemavathy, C Renju Raju, A Kairali, BG Hari Lavanya, ... International Conference on Advances in Electrical and Computer Technologies …, 2021 | | 2021 |
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org