Anupam Chattopadhyay
Anupam Chattopadhyay
Assistant Professor, SCSE, SPMS, NTU, Singapore
Verified email at
TitleCited byYear
High-performance hardware implementation for RC4 stream cipher
SS Gupta, A Chattopadhyay, K Sinha, S Maitra, BP Sinha
IEEE Transactions on Computers 62 (4), 730-743, 2013
RTL processor synthesis for architecture exploration and implementation
O Schliebusch, A Chattopadhyay, R Leupers, G Ascheid, H Meyr, ...
Design, Automation and Test in Europe Conference and Exhibition, 2004 …, 2004
The programmable logic-in-memory (PLiM) computer
PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016 …, 2016
Ingredients of adaptability: a survey of reconfigurable processors
A Chattopadhyay
VLSI Design 2013, 10, 2013
LISA: a uniform ADL for embedded processor modelling, implementation and software toolsuite generation
A Chattopadhyay, H Meyr, R Leupers
Processor Description Languages 1, 95-130, 2008
A design flow for architecture exploration and implementation of partially reconfigurable processors
K Karuri, A Chattopadhyay, X Chen, D Kammler, L Hao, R Leupers, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (10 …, 2008
High-level modelling and exploration of coarse-grained re-configurable architectures
A Chattopadhyay, X Chen, H Ishebabi, R Leupers, G Ascheid, H Meyr
Proceedings of the conference on Design, automation and test in Europe, 1334 …, 2008
Increasing data-bandwidth to instruction-set extensions through register clustering
K Karuri, A Chattopadhyay, M Hohenauer, R Leupers, G Ascheid, H Meyr
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007
Design space exploration of partially re-configurable embedded processors
A Chattopadhyay, W Ahmed, K Karuri, D Kammler, R Leupers, G Ascheid, ...
Proceedings of the conference on Design, automation and test in Europe, 319-324, 2007
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment
J Constantin, L Wang, G Karakonstantis, A Chattopadhyay, A Burg
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
FLEXDET: flexible, efficient multi-mode MIMO detection using reconfigurable ASIP
X Chen, A Minwegen, Y Hassan, D Kammler, S Li, T Kempf, ...
Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual …, 2012
Optimization techniques for ADL-driven RTL processor synthesis
O Schliebusch, A Chattopadhyay, EM Witte, D Kammler, G Ascheid, ...
Rapid System Prototyping, 2005.(RSP 2005). The 16th IEEE International …, 2005
CoARX: a coprocessor for ARX-based cryptographic algorithms
K Shahzad, A Khalid, ZE Rákossy, G Paul, A Chattopadhyay
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, 1-10, 2013
Design and analysis of layered coarse-grained reconfigurable architecture
ZE Rákossy, T Naphade, A Chattopadhyay
Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference …, 2012
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
O Schliebusch, A Chattopadhyay, D Kammler, G Ascheid, R Leupers, ...
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
Wireless Communication and Security Issues for Cyber–Physical Systems and the Internet-of-Things
A Burg, A Chattopadhyay, KY Lam
Proceedings of the IEEE 106 (1), 38-60, 2018
ReVAMP: ReRAM based VLIW architecture for in-memory computing
D Bhattacharjee, R Devadoss, A Chattopadhyay
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 782-787, 2017
Multistate memristive tantalum oxide devices for ternary arithmetic
W Kim, A Chattopadhyay, A Siemon, E Linn, R Waser, V Rana
Scientific reports 6, 36652, 2016
Applying resource sharing algorithms to ADL-driven automatic ASIP implementation
EM Witte, A Chattopadhyay, O Schliebusch, D Kammler, R Leupers, ...
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005
Integrated verification approach during ADL-driven processor design
A Chattopadhyay, A Sinha, D Zhang, R Leupers, G Ascheid, H Meyr
Microelectronics journal 40 (7), 1111-1123, 2009
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