|LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation|
A Chattopadhyay, H Meyr, R Leupers
Processor description languages, 95-132, 2008
|Designing and modeling MPSoC processors and communication architectures|
H Meyr, O Schliebusch, A Wieferink, D Kammler, EM Witte, O Lüthje, ...
Building ASIPS: The Mescal Methodology, 229-280, 2005
|High-performance hardware implementation for RC4 stream cipher|
SS Gupta, A Chattopadhyay, K Sinha, S Maitra, BP Sinha
IEEE Transactions on Computers 62 (4), 730-743, 2013
|RTL processor synthesis for architecture exploration and implementation|
O Schliebusch, A Chattopadhyay, R Leupers, G Ascheid, H Meyr, ...
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
|The programmable logic-in-memory (PLiM) computer|
PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016
|Ingredients of adaptability: a survey of reconfigurable processors|
VLSI Design 2013, 10, 2013
|A design flow for architecture exploration and implementation of partially reconfigurable processors|
K Karuri, A Chattopadhyay, X Chen, D Kammler, L Hao, R Leupers, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (10 …, 2008
|Wireless communication and security issues for cyber–physical systems and the Internet-of-Things|
A Burg, A Chattopadhyay, KY Lam
Proceedings of the IEEE 106 (1), 38-60, 2018
|High-level modelling and exploration of coarse-grained re-configurable architectures|
A Chattopadhyay, X Chen, H Ishebabi, R Leupers, G Ascheid, H Meyr
Proceedings of the conference on Design, automation and test in Europe, 1334 …, 2008
|Increasing data-bandwidth to instruction-set extensions through register clustering|
K Karuri, A Chattopadhyay, M Hohenauer, R Leupers, G Ascheid, H Meyr
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007
|Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment|
J Constantin, L Wang, G Karakonstantis, A Chattopadhyay, A Burg
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
|FLEXDET: flexible, efficient multi-mode MIMO detection using reconfigurable ASIP|
X Chen, A Minwegen, Y Hassan, D Kammler, S Li, T Kempf, ...
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
|Design and analysis of layered coarse-grained reconfigurable architecture|
ZE Rákossy, T Naphade, A Chattopadhyay
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
|Design space exploration of partially re-configurable embedded processors|
A Chattopadhyay, W Ahmed, K Karuri, D Kammler, R Leupers, G Ascheid, ...
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
|Optimization techniques for ADL-driven RTL processor synthesis|
O Schliebusch, A Chattopadhyay, EM Witte, D Kammler, G Ascheid, ...
16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 165-171, 2005
|ReVAMP: ReRAM based VLIW architecture for in-memory computing|
D Bhattacharjee, R Devadoss, A Chattopadhyay
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
|Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits|
R Wille, O Keszocze, M Walter, P Rohrs, A Chattopadhyay, R Drechsler
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 292-297, 2016
|CoARX: a coprocessor for ARX-based cryptographic algorithms|
K Shahzad, A Khalid, ZE Rákossy, G Paul, A Chattopadhyay
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-10, 2013
|A framework for automated and optimized ASIP implementation supporting multiple hardware description languages|
O Schliebusch, A Chattopadhyay, D Kammler, G Ascheid, R Leupers, ...
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
|Combinational logic synthesis for material implication|
A Chattopadhyay, Z Rakosi
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 200-203, 2011