Anupam Chattopadhyay
Anupam Chattopadhyay
Associate Professor, SCSE, SPMS, NTU, Singapore
Verified email at
Cited by
Cited by
LISA: A uniform ADL for embedded processor modeling, implementation, and software toolsuite generation
A Chattopadhyay, H Meyr, R Leupers
Processor description languages, 95-132, 2008
Adversarial attacks and defences: A survey
A Chakraborty, M Alam, V Dey, A Chattopadhyay, D Mukhopadhyay
arXiv preprint arXiv:1810.00069, 2018
Designing and modeling MPSoC processors and communication architectures
H Meyr, O Schliebusch, A Wieferink, D Kammler, EM Witte, O Lüthje, ...
Building ASIPS: The Mescal Methodology, 229-280, 2005
Wireless communication and security issues for cyber–physical systems and the Internet-of-Things
A Burg, A Chattopadhyay, KY Lam
Proceedings of the IEEE 106 (1), 38-60, 2017
The programmable logic-in-memory (PLiM) computer
PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016
High-performance hardware implementation for RC4 stream cipher
SS Gupta, A Chattopadhyay, K Sinha, S Maitra, BP Sinha
IEEE Transactions on Computers 62 (4), 730-743, 2012
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits
R Wille, O Keszocze, M Walter, P Rohrs, A Chattopadhyay, R Drechsler
2016 21st Asia and South Pacific design automation conference (ASP-DAC), 292-297, 2016
RTL processor synthesis for architecture exploration and implementation
O Schliebusch, A Chattopadhyay, R Leupers, G Ascheid, H Meyr, ...
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
Ingredients of Adaptability: A Survey of Reconfigurable Processors.
A Chattopadhyay
VLSI Design, 2013
A blockchain framework for insurance processes
M Raikwar, S Mazumdar, S Ruj, SS Gupta, A Chattopadhyay, KY Lam
2018 9th IFIP International Conference on New Technologies, Mobility and …, 2018
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment
J Constantin, L Wang, G Karakonstantis, A Chattopadhyay, A Burg
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 381-386, 2015
ReVAMP: ReRAM based VLIW architecture for in-memory computing
D Bhattacharjee, R Devadoss, A Chattopadhyay
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
A design flow for architecture exploration and implementation of partially reconfigurable processors
K Karuri, A Chattopadhyay, X Chen, D Kammler, L Hao, R Leupers, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (10 …, 2008
Multistate memristive tantalum oxide devices for ternary arithmetic
W Kim, A Chattopadhyay, A Siemon, E Linn, R Waser, V Rana
Scientific reports 6, 36652, 2016
FLEXDET: flexible, efficient multi-mode MIMO detection using reconfigurable ASIP
X Chen, A Minwegen, Y Hassan, D Kammler, S Li, T Kempf, ...
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
Processor Modeling and Design Tools
A Chattopadhyay, N Dutt, R Leupers, P Mishra
Electronic Design Automation for IC System Design, Verification, and Testing …, 2017
High-level modelling and exploration of coarse-grained re-configurable architectures
A Chattopadhyay, X Chen, H Ishebabi, R Leupers, G Ascheid, H Meyr
Proceedings of the conference on Design, automation and test in Europe, 1334 …, 2008
CoARX: a coprocessor for ARX-based cryptographic algorithms
K Shahzad, A Khalid, ZE Rákossy, G Paul, A Chattopadhyay
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-10, 2013
Design and analysis of layered coarse-grained reconfigurable architecture
ZE Rákossy, T Naphade, A Chattopadhyay
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
Increasing data-bandwidth to instruction-set extensions through register clustering
K Karuri, A Chattopadhyay, M Hohenauer, R Leupers, G Ascheid, H Meyr
2007 IEEE/ACM International Conference on Computer-Aided Design, 166-171, 2007
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