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RAJESH KUMAR BATHIJA
RAJESH KUMAR BATHIJA
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Title
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Year
Low power high speed 16x16 bit multiplier using vedic mathematics
RK Bathija, RS Meena, S Sarkar, R Sahu
International Journal of Computer Applications 59 (6), 2012
562012
Implementation of Convolution and Multipliers in VLSI using Vedic Mathematics
RK Bathija
Kota, 0
Design of Low Power High Speed Adders in McCMOS Technique
S Sharma, R Bathija, RS Meena, A Goswami
Low Power High Speed Complex Multiplier in 45nm Technology
A Goswami, R Bathija, S Sharma
Design of Low Power High Speed 16 bit Adders with McCMOS in 45nm Technology
SSR Bathija, A Goswami
Comparison of High Speed & Low Power Techniques GDI & McCMOS in Full Adder Design
S Sharma, R Bathija, A Goswami
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