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Dr. Jagannath Samanta
Dr. Jagannath Samanta
Associate Professor, Dept. of ECE, Haldia Institute of Technology, India
Verified email at hithaldia.in - Homepage
Title
Cited by
Cited by
Year
Performance analysis of high speed low power carry look-ahead adder using different logic styles
J Samanta, M Halder, BP De
international journal of soft computing and engineering 2 (6), 330-336, 2013
322013
Comparative study for delay & power dissipation of CMOS Inverter in UDSM range
J Samanta, BP De, B Bag, RK Maity
International Journal of Soft Computing and Engineering (IJSCE) 1 (6), 6, 2012
232012
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs
RK Maity, S Tripathi, J Samanta, J Bhaumik
IET Computers & Digital Techniques 14 (5), 210-216, 2020
152020
Fast and power efficient sec-ded and sec-ded-daec codes in iot based wireless sensor networks
S Tripathi, J Jana, J Samanta, J Bhaumik
TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 540-545, 2019
142019
Compact and Power Efficient SEC-DED Codec for Computer Memory
J Samanta, J Bhaumik, S Barman
Microsystem Technologies, 1-10, 2019
142019
Comments on “a novel approach of error detection and correction for efficient energy in wireless networks”
J Samanta, S Tripathi
Multimedia Tools and Applications 78 (6), 7579–7584, 2018
102018
Compact CA-based Single Byte Error Correcting Codec
J Samanta, J Bhaumik, S Barman
IEEE Transactions on Computers 67 (2), 291-298, 2017
102017
FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application
S Tripathi, RK Maity, J Jana, J Samanta, J Bhaumik
Radioelectronics and Communications Systems volume 63, 543–552, 2020
92020
FPGA based modified Karatsuba multiplier
J Samanta, R Sultana, J Bhaumik
Proc. Int. Conf. VLSI Signal Process.(ICVSP) 10, 12, 2014
92014
Design and evaluation of neale-based multi-bit adjacent error-correcting codec for sram
S Tripathi, J Jana, J Samanta, A Raj, D Ranjan, MP Singh
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
82020
An Area and Power Efficient Double Adjacent Error Correcting Parallel Decoder based on (24, 12) Extended Golay Code
RK Maity, J Samanta, J Bhaumik
Conference: 2019 IEEE International Conference on Electrical, Computer and …, 2019
82019
FPGA based area efficient RS (23, 17) codec
J Samanta, J Bhaumik, S Barman
Microsystem Technologies 23, 639-650, 2017
72017
Comprehensive analysis of delay in UDSM CMOS circuits
J Samanta, BP De
IEEE Electronics, Communication and Computing Technologies (ICECCT), 2011 …, 2011
72011
Compact RS (32, 28) encoder
J Samanta, J Bhaumik, S Barman
Intelligent Computing and Applications: Proceedings of the International …, 2015
62015
FPGA and asic implementation of sec-ded-daec codes for sram applications
S Tripathi, J Jana, J Samanta, A Anand, C Kumar, G Raj
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
52020
Performance evaluation of low-cost RGB-depth camera and ultrasonic sensors
A Adhikary, R Vatsa, A Burnwal, J Samanta
International Conference on Communication, Devices and Computing, 331-341, 2019
52019
Comparison of different design techniques of XOR & AND gate using EDA simulation tool
R SULTANA, J SAMANTA
International Journal of VLSI and Embedded Systems (IJVES) 4 (3), 343-349, 2013
52013
Different physical effects in UDSM MOSFET for delay & power estimation: A review
AK Singh, J Samanta
2012 IEEE Students' Conference on Electrical, Electronics and Computer …, 2012
52012
New compact SEC-DED-DAEC code for memory applications
RK Maity, J Samanta, J Bhaumik
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
42020
CA-Based Area Optimized Three Bytes Error Detecting Codes
JAGANNATH SAMANTA, JAYDEB BHAUMIK, SOMA BARMAN
Journal of Cellular Automata 10 (5-6), 409–423, 2015
4*2015
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