Dr. Jagannath Samanta
Dr. Jagannath Samanta
Associate Professor, Dept. of ECE, Haldia Institute of Technology, India
Verified email at hithaldia.in - Homepage
TitleCited byYear
Performance analysis of high speed low power carry look-ahead adder using different logic styles
J Samanta, M Halder, BP De
International Journal of soft computing and engineering (IJSCE) ISSN, 2231-2307, 2013
222013
Comparative study for delay & power dissipation of CMOS Inverter in UDSM range
J Samanta, BP De, B Bag, RK Maity
International Journal of Soft Computing and Engineering (IJSCE) ISSN, 2231-2307, 2012
172012
Comprehensive analysis of delay in UDSM CMOS circuits
J Samanta, BP De
IEEE Electronics, Communication and Computing Technologies (ICECCT), 2011 …, 2011
62011
Compact RS (32, 28) encoder
J Samanta, J Bhaumik, S Barman
Intelligent Computing and Applications, 89-95, 2015
42015
Different physical effects in UDSM MOSFET for delay & power estimation: A review
AK Singh, J Samanta
2012 IEEE Students' Conference on Electrical, Electronics and Computer …, 2012
32012
CA-Based Area Optimized Three Bytes Error Detecting Codes
JAGANNATH SAMANTA, JAYDEB BHAUMIK, SOMA BARMAN
Journal of Cellular Automata 10 (5-6), 409–423, 2015
2*2015
Comments on “VLSI implementation of Reed-Solomon encoder algorithm for communication systems”
J Samanta, J Bhaumik
Radioelectronics and Communications Systems 57 (7), 331-332, 2014
22014
FPGA based modified Karatsuba multiplier
J Samanta, R Sultana, J Bhaumik
International Conference on VLSI and Signal Processing (ICVSP) 10, 12, 2014
22014
Comparison of different design techniques of XOR & AND gate using EDA simulation tool
R SULTANA, J SAMANTA
International Journal of VLSI and Embedded Systems (IJVES) 4 (3), 343-349, 2013
22013
Architecture for programmable generator polynomial based Reed-Solomon encoder and decoder
J Bhaumik, AS Das, J Samanta
International Journal of Soft Computing and Engineering (IJSCE) 2, 395-399, 2013
2*2013
Modified I-V Model for Delay Analysis of UDSM CMOS Circuits
AK Singh, J Samanta, J Bhaumik
Communications, Devices and Intelligent Systems (CODIS), 2012 International …, 2012
22012
CONSTRUCTION AND PERFORMANCE STUDIES OF A PSEUDO-ORTHOGONAL CODE FOR FIBER OPTIC CDMA LAN
RK Maity, J Samanta
International Journal of Soft Computing and Engineering (IJSCE) 1 (6), 196-201, 2012
22012
Comments on “a novel approach of error detection and correction for efficient energy in wireless networks”
J Samanta, S Tripathi
Multimedia Tools and Applications 77, 1-6, 2018
12018
Compact CA-based Single Byte Error Correcting Codec
J Samanta, J Bhaumik, S Barman
IEEE Transactions on Computers 67 (2), 291-298, 2017
12017
FPGA based area efficient RS (23, 17) codec
J Samanta, J Bhaumik, S Barman
Microsystem Technologies 23 (3), 639-650, 2017
12017
Relative Performance Analysis of Different CMOS Full Adder Circuits
M Suman, J Samanta, D Chowdhury, J Bhaumik
International Journal of Computer Applications 114 (6), 8-14, 2015
12015
Performance Analysis of Different Topologies of 1-Bit Full Adder in UDSM Technology
J Samanta, A Patra, D Mishra, R Rashmi, I Kundu, R Koley
International Journal of Innovative Technology and Exploring Engineering …, 2012
1*2012
Delay analysis of UDSM CMOS VLSI circuits
J Samanta, BP De
Procedia Engineering 30, 135-143, 2012
12012
Implementation of a new offset generator block for the low-voltage, low-power self biased threshold voltage extractor circuit
R Dasgupta, D Saha, J Samanta, S Chatterjee, CK Sarkar
Progress in VLSI Design and Test, 156-165, 2012
12012
Compact and Power Efficient SEC-DED Codec for Computer Memory
J Samanta, J Bhaumik, S Barman
Microsystem Technologies, 1-10, 2019
2019
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