Dr. Jagannath Samanta
Dr. Jagannath Samanta
Associate Professor, Dept. of ECE, Haldia Institute of Technology, India
Verified email at hithaldia.in - Homepage
Title
Cited by
Cited by
Year
Performance analysis of high speed low power carry look-ahead adder using different logic styles
J Samanta, M Halder, BP De
International Journal of Soft Computing and Engineering (IJSCE) ISSN, 2231-2307, 2013
322013
Comparative study for delay & power dissipation of CMOS Inverter in UDSM range
J Samanta, BP De, B Bag, RK Maity
International Journal of Soft Computing and Engineering (IJSCE) 1 (6), 6, 2012
172012
Comments on “a novel approach of error detection and correction for efficient energy in wireless networks”
J Samanta, S Tripathi
Multimedia Tools and Applications 78 (6), 7579–7584, 2018
92018
Comprehensive analysis of delay in UDSM CMOS circuits
J Samanta, BP De
IEEE Electronics, Communication and Computing Technologies (ICECCT), 2011 …, 2011
72011
Fast and power efficient sec-ded and sec-ded-daec codes in iot based wireless sensor networks
S Tripathi, J Jana, J Samanta, J Bhaumik
TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 540-545, 2019
52019
Compact CA-based Single Byte Error Correcting Codec
J Samanta, J Bhaumik, S Barman
IEEE Transactions on Computers 67 (2), 291-298, 2017
52017
Compact RS (32, 28) encoder
J Samanta, J Bhaumik, S Barman
Intelligent Computing and Applications, 89-95, 2015
52015
Comparison of different design techniques of XOR & AND gate using EDA simulation tool
R SULTANA, J SAMANTA
International Journal of VLSI and Embedded Systems (IJVES) 4 (3), 343-349, 2013
52013
CA-Based Area Optimized Three Bytes Error Detecting Codes
JAGANNATH SAMANTA, JAYDEB BHAUMIK, SOMA BARMAN
Journal of Cellular Automata 10 (5-6), 409–423, 2015
4*2015
Comments on “VLSI implementation of Reed-Solomon encoder algorithm for communication systems”
J Samanta, J Bhaumik
Radioelectronics and Communications Systems 57 (7), 331-332, 2014
42014
FPGA based modified Karatsuba multiplier
J Samanta, R Sultana, J Bhaumik
International Conference on VLSI and Signal Processing (ICVSP) 10, 12, 2014
42014
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs
RK Maity, S Tripathi, J Samanta, J Bhaumik
IET Computers & Digital Techniques 14 (5), 210-216, 2020
32020
FPGA and asic implementation of sec-ded-daec codes for sram applications
S Tripathi, J Jana, J Samanta, A Anand, C Kumar, G Raj
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
32020
Design and evaluation of neale-based multi-bit adjacent error-correcting codec for sram
S Tripathi, J Jana, J Samanta, A Raj, D Ranjan, MP Singh
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
32020
RS(255, 249) codec based on all primitive polynomials over GF(28)
J Samanta, J Bhaumik, S Barman, SGS Hossain, M Sahoo, S Dutta
Lecture Notes in Electrical Engineering (LNEE) 470, 151-161, 2017
32017
FPGA based area efficient RS (23, 17) codec
J Samanta, J Bhaumik, S Barman
Microsystem Technologies 23 (3), 639-650, 2017
32017
Modified I-V Model for Delay Analysis of UDSM CMOS Circuits
AK Singh, J Samanta, J Bhaumik
Communications, Devices and Intelligent Systems (CODIS), 2012 International …, 2012
32012
Different physical effects in UDSM MOSFET for delay & power estimation: A review
AK Singh, J Samanta
2012 IEEE Students' Conference on Electrical, Electronics and Computer …, 2012
32012
Performance Evaluation of Low-Cost RGB-Depth Camera and Ultrasonic Sensors
A Adhikary, R Vatsa, A Burnwal, J Samanta
Proceedings of the 2nd International Conference on Communication, Devices …, 2020
22020
Modified Karatsuba multiplier for key equation solver in RS Code
J Samanta, J Bhaumik, S Barman
Radioelectronics and Communications Systems 58 (10), 452-461, 2015
22015
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Articles 1–20