| Dual material double-layer gate stack SON MOSFET: A novel architecture for enhanced analog performance—Part I: Impact of gate metal workfunction engineering P Kasturi, M Saxena, M Gupta, RS Gupta IEEE transactions on electron devices 55 (1), 372-381, 2007 | 45 | 2007 |
| Dual-material double-layer gate stack SON MOSFET: A novel architecture for enhanced analog performance—Part II: Impact of gate-dielectric material engineering P Kasturi, M Saxena, M Gupta, RS Gupta IEEE transactions on electron devices 55 (1), 382-387, 2007 | 22 | 2007 |
| Robust and secure digital image watermarking technique using Arnold transform and memristive chaotic oscillators K Sehra, S Raut, A Mishra, P Kasturi, S Wadhera, GJ Saxena, M Saxena IEEE Access 9, 72465-72483, 2021 | 19 | 2021 |
| Modeling and simulation of STacked Gate Oxide (STGO) architecture in silicon-on-nothing (SON) MOSFET P Kasturi, M Saxena, RS Gupta Solid-state electronics 49 (10), 1639-1648, 2005 | 13 | 2005 |
| Multilayer perceptron–random forest based hybrid machine learning–neural network model for GaN high electron mobility transistor's parameter estimations A Mishra, S Raut, K Sehra, RP Singh, S Wadhera, P Kasturi, GJ Saxena, ... International Journal of RF and Microwave Computer‐Aided Engineering 32 (7 …, 2022 | 4 | 2022 |
| Memristor based cryptographic information processing for secured communication systems A Mishra, K Sehra, S Sahil, A Joshi, P Kasturi, M Saxena 2020 5th International Conference on Devices, Circuits and Systems (ICDCS …, 2020 | 4 | 2020 |
| Interplay Between γ–Ray Irradiation and 3DEG for Dosimeter Applications K Sehra, V Kumari, P Kasturi, M Gupta, M Mishra, DS Rawal, M Saxena IEEE Access 10, 25811-25827, 2022 | 2 | 2022 |
| Secure digital image watermarking using memristor-based hyperchaotic circuit Sonam, K Sehra, RP Singh, S Singh, S Wadhera, P Kasturi, GJ Saxena, ... The Visual Computer 39 (10), 4459-4485, 2023 | 1 | 2023 |
| Secure digital image watermarking using memristor-based hyperchaotic circuit Sonam, K Sehra, RP Singh, S Singh, S Wadhera, P Kasturi, GJ Saxena, ... VISUAL COMPUTER, 2022 | 1 | 2022 |
| NI Multisim andExperimental Validation Implitation of Ratioed Logic Gates Using Memristor RK Pandey, A Gupta, D Goel, P Kasturi, MA Wagh, M Saxena | 1 | 2016 |
| Simulation and Experimental Demonstration ofLow-/High-Pass Filter using Memristors K Sehra, GK Shakya, P Kasturi, MA Wagh, M Saxena | 1 | 2016 |
| Interplay between 𝜸𝜸–ray Irradiation and 3DEG for Dosimeter Applications P Kasturi, M Gupta, M Mishra | | |
