| Process variation tolerant 9T SRAM bitcell design GK Reddy, K Jainwal, J Singh, SP Mohanty Thirteenth International Symposium on Quality Electronic Design (ISQED), 493-497, 2012 | 20 | 2012 |
| A Three-Phase, One-Tap High Background Light Subtraction Time-of-Flight Camera C Anand, K Jainwal, M Sarkar IEEE Transactions on Circuits and Systems I: Regular Papers, 2019 | 9 | 2019 |
| Analysis and validation of low-frequency noise reduction in MOSFET circuits using variable duty cycle switched biasing K Jainwal, M Sarkar, K Shah IEEE Journal of the Electron Devices Society 6, 420-431, 2018 | 6 | 2018 |
| Low frequency noise reduction using multiple transistors with variable duty cycle switched biasing K Jainwal, K Shah, M Sarkar IEEE Journal of the Electron Devices Society 3 (6), 481-486, 2015 | 6 | 2015 |
| Design of a hybrid ring oscillator at 1.5/3.0 GHz with low power supply sensitivity V Sharma, K Jainwal, A Tripathi 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 567-570, 2016 | 5 | 2016 |
| 1/ Noise Reduction Using In-Pixel Chopping in CMOS Image Sensors K Jainwal, C Anand, M Sarkar IEEE Solid-State Circuits Letters 1 (6), 146-149, 2018 | 4 | 2018 |
| A high background light subtraction circuit for long range time-of-flight cameras C Anand, K Jainwal, M Sarkar 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 487-490, 2016 | 4 | 2016 |
| A 125-klx background light subtraction architecture for 2-D and time-of-flight 3-D cameras C Anand, N Priyadarshini, K Jainwal, M Sarkar IEEE Transactions on Electron Devices 65 (9), 3823-3830, 2018 | 3 | 2018 |
| A SPAD Based dToF Pixel with Log/Linear Multi-mode Operation for LiDAR Applications S Faizan, M Bisen, K Jainwal 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 1 | 2023 |
| A 280-μ V Temporal Noise, 76-dB Dynamic Range CMOS Image Sensor With an In-Pixel Chopping-Based Low-Frequency Noise Reduction Technique K Jainwal, M Sarkar IEEE Transactions on Electron Devices 70 (3), 1134-1142, 2023 | 1 | 2023 |
| Phase noise reduction in CMOS LC oscillators using tail noise shaping and Gm3 boosting K Jainwal, J Mukherjee 2008 International Conference on Electrical and Computer Engineering, 302-305, 2008 | 1 | 2008 |
| Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel M Bisen, K Jainwal, N Khanna 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| Tau-cell-based Analog Silicon Retina with Spatio-Temporal Filtering and Contrast Gain Control P Phillip, K Jainwal, A van Schaik, CS Thakur IEEE Transactions on Biomedical Circuits and Systems, 2023 | | 2023 |
| A Novel Active Pixel Sensor Architecture with In-Pixel Chopping and Switched Biasing to Reduce the Low-Frequency Noise K Jainwal, M Sarkar 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
| A 15-nW 14-ppm/° C 1.18 V startup-less bandgap-based voltage regulator K Jainwal, KK Kumar, G Chowdary, S Chatterjee 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
| Low frequency noise reduction techniques for cmos image sensors K Jainwal Delhi, 2019 | | 2019 |
| Low-Frequency Noise Reduction Using In-Pixel Chopping To Enhance The Dynamic Range of a CMOS Image Sensor K Jainwal arXiv preprint arXiv:1811.11020, 2018 | | 2018 |
| Analysis and validation of low-frequency noise reduction in MOSFET circuits using variable duty cycle switched biasing K Shah IEEE Journal of the Electron Devices Society, 2017 | | 2017 |
Chandani AnandSamsung Semiconductor R&D Institute India, Research Scholar at IIT Delhi IndiaVerified email at ee.iitd.ac.in
