| Design of FinFET-based energy efficient pass-transistor adiabatic logic for ultra-low power applications BP Bhuvana, VSK Bhaaskaran Microelectronics Journal 92, 104601, 2019 | 13 | 2019 |
| Positive feedback symmetric adiabatic logic against differential power attack BP Bhuvana, BVS Kanchana 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 11 | 2018 |
| Design of reversible adders using a novel reversible BKG gate BP Bhuvana, KB VS 2016 Online International Conference on Green Engineering and Technologies …, 2016 | 10 | 2016 |
| Adiabatic Logic Circuits Using FinFETs and CMOS–A Review BP Bhuvana, BR Manohar, VS Kanchana Bhaaskaran International Journal of Engineering and Technology 8 (2), 1256-1270, 2016 | 9 | 2016 |
| Quantum cost optimization of reversible adder/subtractor using a novel reversible gate BP Bhuvana, VS Kanchana Bhaaskaran Innovations in Electronics and Communication Engineering: Proceedings of the …, 2018 | 6 | 2018 |
| Design and analysis of low power and high speed FinFET based hybrid full adder/subtractor circuit (FHAS) E Ramkumar, D Gracin, P Rajkamal, BP Bhuvana, VSK Bhaaskaran 2020 IEEE International Symposium on Smart Electronic Systems (iSES …, 2020 | 5 | 2020 |
| Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems BP Bhuvana, VSK Bhaaskaran AEU-International Journal of Electronics and Communications 108, 127-140, 2019 | 4 | 2019 |
| Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET BP Bhuvana, VSK Bhaaskaran Procedia computer science 115, 166-173, 2017 | 4 | 2017 |
| A novel adiabatic logic for low power VLSI circuit design and power optimization using FinFET BP Bhuvana, VS Kanchana Bhaaskaran VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 3 | 2018 |
| Standard cell characterization for reversible logic BP Bhuvana, BR Manohar, VSK Bhaaskaran 2016 International Conference on Micro-Electronics and Telecommunication …, 2016 | 3 | 2016 |
| Analysis of FinFET based Adiabatic Circuits for the Design of Arithmetic Structures BP Bhuvana, VS Kanchana Bhaaskaran Journal of Circuits, Systems and Computers 29 (1), 2020 | 2 | 2020 |
| VLSI Design: Circuits, Systems and Applications: Select Proceedings of ICNETS2, Volume V J Li, AR Sankar, PAS Beulet Springer Singapore, 2018 | 2 | 2018 |
| Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit AL Bhalerao, A Mane, K Pensenwar, BP Bhuvana, AA Angeline, ... Journal of Physics: Conference Series 1716 (1), 012033, 2020 | 1 | 2020 |
| Design and Analysis of FinFET Based CSCPAL Low Power Adder KG Jayashree, BP Bhuvana, KB VS 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | | 2019 |
| Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits BP Bhuvana, VSK Bhaaskaran 2019 International Conference on Smart Systems and Inventive Technology …, 2019 | | 2019 |
| LOW POWER 64-BIT CARRY SELECT ADDER USING MODIFIED EXNOR BLOCK B Srinivasa Raghavan, BP Bhuvana, VS Kanchana Bhaaskaran ARPN Journal of Engineering and Applied Sciences 10 (22), 2015 | | 2015 |
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org
V S Kanchana BhaaskaranVICE CHANCELLOR, VIT VELLOREVerified email at ieee.org