satish chandra tiwari
satish chandra tiwari
Verified email at cadence.com
Title
Cited by
Cited by
Year
An area and power efficient design of single edge triggered D-flip flop
M Sharma, A Noor, SC Tiwari, K Singh
2009 International Conference on Advances in Recent Technologies in …, 2009
292009
A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product
K Singh, SC Tiwari, M Gupta
The Scientific World Journal 2014, 2014
92014
Effect of different insect hosts on biology and predation efficiency of Eocanthecona furcellata Wolff(Hemiptera: Pentatomidae)
S Tiwari, RP Maurya, AK Pandey
International Quarterly Journal of Life Sciences. The Bioscan 12, 193-197, 2017
62017
A high performance flip flop for low power low voltage systems
K Singh, SC Tiwari, M Gupta
Information and Communication Technologies (WICT), 2011 World Congress on …, 2011
62011
A low power high density double edge triggered flip flop for low voltage systems
SC Tiwari, K Singh, M Gupta
2010 International Conference on Advances in Recent Technologies in …, 2010
52010
Method and system for automated design of an integrated circuit using configurable cells
K Singh, SC Tiwari, M Gupta
US Patent App. 14/438,179, 2015
32015
A closed-loop ASIC design approach based on logical effort theory and artificial neural networks
K Singh, SC Tiwari, M Gupta
Integration 69, 10-22, 2019
2*2019
State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems
K Singh, SC Tiwari, M Gupta
Design and Modeling of Low Power VLSI Systems, 166-198, 2016
12016
Logical effort based automated transistor width optimization methodology
SC Tiwari, A Gupta, K Singh, M Gupta
Information and Communication Technologies (WICT), 2011 World Congress on …, 2011
12011
A novel methodology for flip-flop optimization and characterization in NOC design space
SC Tiwari, K Singh, M Gupta
Information and Communication Technologies (WICT), 2011 World Congress on …, 2011
12011
Method and system for automated design of an integrated circuit using configurable cells
MG Satish Chandra TIWARI, Kunwar SINGH
WO Patent App. PCT/IB2013/059,646, 2014
2014
Intellectual Property Rights in Semi-Conductor Industries: An Indian Perspective
SC Tiwari, M Gupta, MA Khan, AQ Ansari
Business Strategies and Approaches for Effective Engineering Management, 97-110, 2013
2013
A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits
K Singh, SC Tiwari, M Gupta
International Journal of Circuits and Architecture Design 1 (1), 89-113, 2013
2013
Automated transistor width optimisation algorithms for digital circuits
SC Tiwari, K Singh, M Gupta
International Journal of Embedded Systems 5 (1-2), 44-52, 2013
2013
Standard test bench for optimization and characterization of combinational circuits
SC Tiwari, MA Khan, K Singh, A Sangal
2012 IEEE International Conference on Signal Processing, Computing and …, 2012
2012
Design and development of circuit optimizer using TCl and SPECTREMDL(SPICE) interface
SC Tiwari, K Singh, M Gupta
Information and Communication Technologies (WICT), 2011 World Congress on …, 2011
2011
ULTRA LOW POWER, SINGLE EDGE TRIGGERED D-FLIP/FLOP (STATIC AND DYNAMIC) WITH REDUCED TRANSISTORS
SC Tiwari, K Singh, M Kumar
2008
Intellectual Property Rights in Semi-Conductor Industries
SC Tiwari, M Gupta, MA Khan, AQ Ansari
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