Sneh Saurabh
Title
Cited by
Cited by
Year
Novel attributes of a dual material gate nanoscale tunnel field-effect transistor
S Saurabh, MJ Kumar
IEEE transactions on Electron Devices 58 (2), 404-410, 2010
3902010
Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis
S Saurabh, MJ Kumar
Japanese Journal of Applied Physics 48 (6R), 064503, 2009
1352009
Fundamentals of tunnel field-effect transistors
S Saurabh, MJ Kumar
CRC press, 2016
1242016
Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability
S Saurabh, MJ Kumar
IEEE transactions on device and materials reliability 10 (3), 390-395, 2010
682010
Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis
S Garg, S Saurabh
Superlattices and Microstructures 113, 261-270, 2018
532018
Resistive random access memory: A review of device challenges
V Gupta, S Kapur, S Saurabh, A Grover
IETE Technical Review 37 (4), 377-390, 2020
302020
Improving the scalability of SOI-Based tunnel FETs using ground plane in buried oxide
S Garg, S Saurabh
IEEE Journal of the Electron Devices Society 7, 435-443, 2019
142019
Realizing logic functions using single double-gate tunnel FETs: A simulation study
S Banerjee, S Garg, S Saurabh
IEEE Electron Device Letters 39 (5), 773-776, 2018
112018
Method and apparatus for comprehension of common path pessimism during timing model extraction
S Saurabh, N Kumar, I Keller
US Patent 8,938,703, 2015
102015
Dopingless 1T DRAM: Proposal, design, and analysis
A James, S Saurabh
IEEE Access 7, 88960-88969, 2019
92019
Implementing logic functions using independently-controlled gate in double-gate tunnel FETs: Investigation and analysis
S Garg, S Saurabh
IEEE Access 7, 117591-117599, 2019
72019
Method and apparatus for efficient generation of compact waveform-based timing models
S Saurabh, N Kumar
US Patent 9,727,676, 2017
62017
Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor
S Garg, S Saurabh
IEEE Open Journal of Nanotechnology 1, 100-108, 2020
52020
Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs
S Saurabh, N Kumar
US Patent 10,255,403, 2019
52019
A practical methodology to compress technology libraries using recursive polynomial representation
S Saurabh, P Mittal
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
52018
Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors
S Garg, S Saurabh
IEEE Journal of the Electron Devices Society 8, 1001-1009, 2020
42020
Timing closure problem: Review of challenges at advanced process nodes and solutions
S Saurabh, H Shah, S Singh
IETE Technical Review, 2018
42018
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning
OVSS Ram, S Saurabh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
32020
Implementation of Boolean Functions Using Tunnel Field-Effect Transistors
S Garg, S Saurabh
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020
12020
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate
S Poria, S Garg, S Saurabh
2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6, 2020
12020
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