| Performance Analysis of Secure Integrated Circuits using Blowfish Algorithm VK Swamy, GB Dr Prabhu Global Journal of Computer Science and Technology Network, Web & Security 13 …, 2013 | 5 | 2013 |
| Design of High Speed AES Algorithm MC Mohan, VK Swamy, DT Srinivasulu International Conference on Electronics and Communication Engineering (ICECE …, 2012 | 4 | 2012 |
| High Throughput and High Speed Blowfish Algorithm for Secure Integrated Circuits VK Swamy, GB Dr Prabhu Ana le. Seria Informatică 12, 0 | 4 | |
| VLSI Design flow for Secure Integrated Circuits based on DES, TDES, AES and Blowfish Algorithms and their performance VK Swamy, P Benakop International Journal of Engineering & Technology 7 (2.16), 94-97, 2018 | 3 | 2018 |
| Implementation of a digital design flow for DPA secure WDDL Cryptoprocessor using Blowfish Algorithm VK Swamy, DPG Benakop, P Sandeep Libyan Arab International Conference on Electrical and Electronic …, 2010 | 3 | 2010 |
| Predominance of Blowfish over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits using Verilog HDL VK Swamy, P Benakop International Journal of Network Security & Its Applications (IJNSA), ISSN …, 2017 | 2 | 2017 |
| Predominance of blowfish over triple data encryption standard symmetric key algorithm for secure integrated circuits using verilog hdl V Kumara Swamy Available at SSRN 3656150, 2017 | 1 | 2017 |
| Design and Optimization of Low Power and High-Performance CMOS Circuits NK Anushkannan, VK Swamy, KA Munaf, K Subramani, T Sathish 2023 4th International Conference on Smart Electronics and Communication …, 2023 | | 2023 |
| URBAN WATER QUALITY PREDICTION K Sahit, PN Reddy, VK Swamy International Research Journal of Modernization in Engineering Technology …, 2022 | | 2022 |
| HIGH THROUGHPUT AND HIGH SPEED BLOWFISH ALGORITHM FOR SECURE INTEGRATED CIRCUITS. P Benakop Annals. Computer Science Series 12 (1), 2014 | | 2014 |
| High Speed VLSI Architecture of Wallace Tree Multiplier Utilised in FIR Filter VK Swamy, RVSV Vardhan, A Shravanthi, BS Krishna | | |
| IJNSA 03 K Swamy, P Benakop | | |
| Implementation of Pll in Rf Transceiver using SPI and Uart Protocols PB V Kumara Swamy | | |
| Semicustom ASIC Design of Low Power and Area efficient Carry Select Parallel Adder used for Secure Integrated Circuits PB V Kumara Swamy | | |
| HIGH THROUGHPUT AND HIGH SPEED BLOWFISH ALGORITHM FOR SECURE INTEGRATED CIRCUITS V Kumara Swamy, P Benakop | | |
| VLSI Design flow for Secure Integrated Circuits based on DES, TDES, AES and Blowfish Algorithms and their performance metrics | | |
Prof Prabhu G BenakopPrincipal,Methodist College of Engineering and TechnologyVerified email at ieee.org
