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Dr. G. Amuthavalli
Dr. G. Amuthavalli
Associate Professor, Sri Venkateshwaraa College of Engineering & Technology, Puducherry
Verified email at ifet.ac.in
Title
Cited by
Cited by
Year
Secure and load‐balanced routing protocol in wireless sensor network or disaster management
U Palani, G Amuthavalli, V Alamelumangai
IET Information Security 14 (5), 513-520, 2020
222020
Analysis and design of subthreshold leakage power-aware ripple carry adder at circuit-level using 90nm technology
G Amuthavalli, R Gunasundari
Procedia Computer Science 48, 660-665, 2015
72015
Analysis of 16-bit Carry Look Ahead Adder-a Subthreshold Leakage Power Perspective
G Amuthavalli, R Gunasundari
International Journal of Engineering and Applied Sciences 10 (6), 2015
52015
Notice of Violation of IEEE Publication Principles: Sketch Based Image Retrieval System Using ExHoG
G Amuthavalli, GP Sunder, U Palani, D Saravanan, D StalinDavid, ...
2021 International Conference on System, Computation, Automation and …, 2021
42021
Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits
G Amuthavalli, R Gunasundari
2018 IEEE International Conference on System, Computation, Automation and …, 2018
32018
Energy-based Localization of IWSN in Biotechnology Industrial Applications
U Palani, G Amuthavalli, C Prakash, C Suresh
Research Journal of Biotechnology 2 (Special Issue 2), 61-72, 2017
22017
Leakage Power Reduction in 32-bit Digital Comparator using Modified Power Gating Technique
G Amuthavalli, R Gunasundari, A Nijandan
Applied Mechanics and Materials 742, 741-744, 2015
22015
Investigation on the Impact of Supply Voltage in Subthreshold Leakage Mitigation
G Amuthavalli, R Gunasundari, U Palani
2020 International Conference on System, Computation, Automation and …, 2020
2020
Investigation on the Impact of Supply Voltage in Subthreshold Leakage Mitigation
PU Amuthavalli. G, Gunasundari. R
IEEE - International Conference on System, Computation, Automation and …, 2020
2020
Power-Efficient 32 Bit Adder-Subtractor with Integrated Logic Design and Leakage Mitigation Techniques
RG U.Palani1, G. Amuthavalli
International Journal of Engineering and Advanced Technology (IJEAT) 8 (5 …, 2019
2019
Design and analysis of subthreshold leakage reduction in CMOS combinational circuits
G Amuthavalli
Department of Electronics and Communication Engineering, PEC, PU, 2018
2018
Standby Mode Subthreshold Leakage Power Analysis in Digital Circuits with Variations in Temperature
G Amuthavalli, R Gunasundari
International Journal of Computer Science and Information Security 14 …, 2016
2016
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