| An improved design of a multiplier using reversible logic gates HR Bhagyalakshmi, MK Venkatesha International journal of engineering science and technology 2 (8), 3838-3845, 2010 | 165 | 2010 |
| Novel low power comparator design using reversible logic gates AN Nagamani, HV Jayashree, HR Bhagyalakshmi Indian Journal of Computer Science and Engineering (IJCSE) 2 (4), 566-574, 2011 | 101 | 2011 |
| Optimized reversible BCD adder using new reversible logic gates HR Bhagyalakshmi, MK Venkatesha arXiv preprint arXiv:1002.3994, 2010 | 81 | 2010 |
| Optimized multiplier using reversible multi-control input toffoli gates HR Bhagyalakshmi, MK Venkatesha International Journal of VLSI Design & Communication Systems 3 (6), 27, 2012 | 35 | 2012 |
| Design of parity preserving logic based fault tolerant reversible arithmetic logic unit R Saligram, SS Hegde, SA Kulkarni, HR Bhagyalakshmi, MK Venkatesha arXiv preprint arXiv:1307.3690, 2013 | 22 | 2013 |
| Design of sequential circuit elements using reversible logic gates HR Bhagyalakshmi, MK Venkatesha World Applied Programming 2 (5), 263-271, 2012 | 19 | 2012 |
| Design of fault tolerant reversible multiplexer based multi-boolean function generator using parity preserving gates R Saligram, SS Hegde, SA Kulkarni, HR Bhagyalakshmi, MK Venkatesha International Journal of Computer Applications 66 (19), 2013 | 18 | 2013 |
| Design of a multifunction BVMF reversible logic gate and its applications HR Bhagyalakshmi, MK Venkatesha International Journal of Computer Applications 32 (3), 36-41, 2011 | 18 | 2011 |
| Modified Toffoli gate and its applications in designing components of reversible arithmetic and logic unit HV Jayashree, AN Nagamani, HR Bhagyalakshmi International Journal of Advanced Research in Computer Science and Software …, 2012 | 10 | 2012 |
| Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates HR Bhagyalakshmi, MK Venkatesha International journal on computer science and Engineering 3 (4), 1439-1449, 2011 | 8 | 2011 |
| Novel Design of one digit high speed Carry select BCD Subtractor using Reversible logic gates‖ M Sudharshan, HR Bhagyalakshmi, MK Venkatesha International Journal of Emerging Technology and Advanced Engineering (ISSN …, 2012 | 5 | 2012 |
| Toffoli cascade synthesis of an optimized two-bit comparator HR Bhagyalakshmi, MK Venkatesha Emerging Research in Electronics, Computer Science and Technology …, 2014 | 1 | 2014 |
| An Optimized Multiplier Using Reversible Logic Gates. HR Bhagyalakshmi, MK Venkatesha International Journal of Advanced Research in Computer Science 3 (4), 2012 | | 2012 |
| Design of ALU using Reversible Logic Gates PS N Srinivasa Rao, H.R.Bhagyalakshmi International Conference on Computing, Communications, Systems …, 2012 | | 2012 |
| Optimized Reversible carry select BCD adders using Reversible logic gates HR Bhagyalakshmi, MK Venkatesha | | |
