| Nanowire reconfigurable FET as biosensor: Based on dielectric modulation approach P Saha, DK Dash, SK Sarkar Solid-State Electronics 161, 107637, 2019 | 33 | 2019 |
| 3D modelling and performance analysis of dual material tri-gate tunnel field effect transistor P Saha, S Sarkhel, SK Sarkar IETE Technical review 36 (2), 117-129, 2019 | 18 | 2019 |
| Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET DK Dash, P Saha, SK Sarkar Journal of Computational Electronics 17, 181-191, 2018 | 17 | 2018 |
| Drain current characterization of dielectric modulated split gate TFET for bio-sensing application P Saha, SK Sarkar Materials Science in Semiconductor Processing 124, 105598, 2021 | 14 | 2021 |
| Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET P Saha, S Sarkhel, SK Sarkar Journal of Computational Electronics 16, 648-657, 2017 | 13 | 2017 |
| Drain current modeling of proposed dual material elliptical Gate-All-Around heterojunction TFET for enhanced device performance P Saha, SK Sarkar Superlattices and Microstructures 130, 194-207, 2019 | 12 | 2019 |
| Investigation of gate‑engineered heterostructure tunnel field effect transistor as a label‑free biosensor: a compact study AKPS Rittik Ghosh Applied Physics A, Material Science and Processing, 2023 | 8* | 2023 |
| Modeling of dual gate material hetero-dielectric strained PNPN TFET for improved ON current T Kumari, P Saha, DK Dash, SK Sarkar Journal of Materials Engineering and Performance 27, 2747-2753, 2018 | 8 | 2018 |
| 2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET P Saha, P Banerjee, SK Sarkar Superlattices and Microstructures 118, 16-28, 2018 | 8 | 2018 |
| Exploring the short-channel characteristics of asymmetric junctionless double-gate silicon-on-nothing MOSFET P Saha, P Banerjee, DK Dash, SK Sarkar Journal of Materials Engineering and Performance 27, 2708-2712, 2018 | 8 | 2018 |
| 3D Modeling based Performance Analysis of Gate Engineered Trigate SON TFET with SiO2/HfO2 stacked gate oxide P Saha, S Sarkhel, P Banerjee, SK Sarkar 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 8 | 2018 |
| Impact of self-heating and nano-gap filling factor on AlGaAs/GaAs junction-less DG-MOSFET based biosensor for early stage diagnostics D Sen, B Goswami, A Dey, P Saha, SK Sarkar 2020 IEEE Region 10 Symposium (TENSYMP), 662-665, 2020 | 6 | 2020 |
| Impact of trapped interface charges on short channel characteristics of WFE high-K SOI MOSFET P Saha, P Banerjee, DK Dash, SK Sarkar 2019 Devices for Integrated Circuit (DevIC), 118-123, 2019 | 6 | 2019 |
| Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET P Saha, S Sarkhel, SK Sarkar Journal of Electronic Materials 48, 3823-3832, 2019 | 5 | 2019 |
| Analytical modeling and performance analysis of graded channel strained dual-material double gate MOSFET P Banerjee, P Saha, DK Dash, A Ghosh, SK Sarkar 2018 4th International Conference on Computing Communication and Automation …, 2018 | 5 | 2018 |
| 3-D analytical modeling of dual-metal front-gate stack tri-gate SON-TFET with graded channel engineering DK Dash, P Saha, A Mahajan, SK Sarkar 2017 IEEE Calcutta Conference (CALCON), 199-204, 2017 | 5 | 2017 |
| A quasi-two-dimensional analytical threshold voltage model for short-channel junctionless double-gate nanoscale SON MOSFET S Basak, P Saha, SK Sarkar IEEE Proceedings of International Conference on Recent Advances in …, 2014 | 5 | 2014 |
| Interface trap charge induced threshold voltage modeling of WFE high-K SOI MOSFET P Saha, P Banerjee, DK Dash, SK Sarkar Silicon 12, 2893-2900, 2020 | 4 | 2020 |
| 3D analytical modeling and electrical characteristics analysis of gate-engineered SiO2/HfO2-stacked tri-gate TFET DK Dash, P Saha, A Mahajan, T Kumari, SK Sarkar Indian journal of physics 94, 219-232, 2020 | 4 | 2020 |
| Surface potential based analytical modeling of graded channel strained high-k gate stack dual-material double gate MOSFET P Banerjee, P Saha, DK Dash, SK Sarkar 2019 Devices for Integrated Circuit (DevIC), 240-244, 2019 | 4 | 2019 |
Subir Kumar SarkarProfessor, Department of ETCE, Jadavpur UniversityVerified email at etce.jdvu.ac.in
