Deepak Majeti
Title
Cited by
Cited by
Year
Efficient mapping of irregular C++ applications to integrated GPUs
R Barik, R Kaleem, D Majeti, BT Lewis, T Shpeisman, C Hu, Y Ni, ...
Proceedings of Annual IEEE/ACM International Symposium on Code Generation†…, 2014
292014
Compiler-Driven Data Layout Transformation for Heterogeneous Platforms
D Majeti, R Barik, J Zhao, G Max, S Vivek
International Workshop on Algorithms, Models and Tools for Parallel†…, 2013
272013
Optimization of lattice Boltzmann simulation with graphics-processing-unit parallel computing and the application in reservoir characterization
C Chen, Z Wang, D Majeti, N Vrvilo, T Warburton, V Sarkar, G Li
SPE Journal 21 (04), 1,425-1,435, 2016
182016
Automatic data layout generation and kernel mapping for cpu+ gpu architectures
D Majeti, KS Meel, R Barik, V Sarkar
Proceedings of the 25th International Conference on Compiler Construction†…, 2016
172016
Heterogeneous work-stealing across CPU and DSP cores
V Kumar, A SbÓrlea, A Jayaraj, Z Budimlić, D Majeti, V Sarkar
2015 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2015
112015
Heterogeneous Habanero-C (H2C): a portable programming model for heterogeneous processors
D Majeti, V Sarkar
2015 IEEE International Parallel and Distributed Processing Symposium†…, 2015
102015
Extended Task Queuing: Active Messages for Heterogeneous Systems
M LeBeane, B Potter, A Pan, A Dutu, V Agarwala, W Lee, D Majeti, ...
SC16: International Conference for High Performance Computing, Networking†…, 2016
82016
Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications
D Majeti, A Pasalapudi, K Yalamanchili
2009 Second International Conference on Emerging Trends in Engineering†…, 2009
82009
Adha: Automatic data layout framework for heterogeneous architectures
D Majeti, KS Meel, R Barik, V Sarkar
2014 23rd International Conference on Parallel Architecture and Compilation†…, 2014
62014
Design of optimal architectures using homogeneous routers for application specific network on chip
K Yalamanchili, A Pasalapudi, D Majeti, V Sunitha
2008 First International Conference on Emerging Trends in Engineering and†…, 2008
62008
Power aware work stealing
MW LeBeane, D Majeti, M Breternitz
US Patent 10,089,155, 2018
22018
Lightweight dynamic task creation and scheduling on the Intel Single Chip Cloud (SCC) processor
D Majeti
Proceedings of the Fourth Workshop on Programming Language Approaches to†…, 2011
12011
Portable Programming Models for Heterogeneous Platforms
D Majeti
2015
On the arithmetic of one del Pezzo surface over the field with three elements
N Kozin, D Majeti
arXiv preprint arXiv:1409.7856, 2014
2014
Improving speculative loop parallelization via selective squash and speculation reuse
SS Ananthramu, D Majeti, SK Aggarwal, M Chaudhuri
Proceedings of the 19th International Conference on Parallel Architectures†…, 2010
2010
Design of optimal architectures for application specific network on chip
A Pasalapudi, D Majeti
Dhirubhai Ambani Institute of Information and Communication Technology, 2008
2008
FPGAs (ReConFig) Additional Reviewers
F Hategekimana, A Haron, A Arış, A Wild, A…DM Martins, ...
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