sathe chaitanya
sathe chaitanya
Intel Corporation
Verified email at ks.uiuc.edu
Title
Cited by
Cited by
Year
Computational investigation of DNA detection using graphene nanopores
C Sathe, X Zou, JP Leburton, K Schulten
ACS nano 5 (11), 8842-8851, 2011
1942011
Detection and quantification of methylation in DNA using solid-state nanopores
J Shim, GI Humphreys, BM Venkatesan, JM Munz, X Zou, C Sathe, ...
Scientific reports 3 (1), 1-8, 2013
1782013
Graphene quantum point contact transistor for DNA sensing
A Girdhar, C Sathe, K Schulten, JP Leburton
Proceedings of the National Academy of Sciences 110 (42), 16748-16753, 2013
862013
A novel table-based approach for design of FinFET circuits
RA Thakker, C Sathe, AB Sachid, MS Baghini, VR Rao, MB Patil
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
312009
Electronic detection of dsDNA transition from helical to zipper conformation using graphene nanopores
C Sathe, A Girdhar, JP Leburton, K Schulten
Nanotechnology 25 (44), 445105, 2014
192014
Tunable graphene quantum point contact transistor for DNA detection and characterization
A Girdhar, C Sathe, K Schulten, JP Leburton
Nanotechnology 26 (13), 134005, 2015
182015
A table-based approach to study the impact of process variations on FinFET circuit performance
RA Thakker, C Sathe, MS Baghini, MB Patil
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
142010
Assessment of SET logic robustness through noise margin modeling
C Sathe, SS Dan, S Mahapatra
IEEE transactions on electron devices 55 (3), 909-915, 2008
122008
Gate-modulated graphene quantum point contact device for DNA sensing
A Girdhar, C Sathe, K Schulten, JP Leburton
Journal of computational electronics 13 (4), 839-846, 2014
102014
Automated design and optimization of circuits in emerging technologies
RA Thakker, C Sathe, AB Sachid, MS Baghini, VR Rao, MB Patil
2009 Asia and South Pacific Design Automation Conference, 504-509, 2009
72009
ACS Nano 5, 8842 (2011)
C Sathe, X Zou, JP Leburton, K Schulten
Crossref, ISI, 0
7
Modeling and analysis of noise margin in set logic
C Sathe, S Mahapatra
20th International Conference on VLSI Design held jointly with 6th …, 2007
22007
Computational Investigation of Graphene nano pore DNA detection
C Sathe, X Zou, JP Leburton, K Schulten
Biophysical Journal 102 (3), 204a, 2012
12012
Computational study of graphene nanopore sensor for DNA sensing
C Sathe
University of Illinois at Urbana-Champaign, 2014
2014
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design …
AB Sachid, RA Thakker, C Sathe, MS Baghini, DK Sharma, VR Rao, ...
2010 11th International Symposium on Quality Electronic Design (ISQED), 713-720, 2010
2010
A Functional Unit and Register Binding Algorithm for Interconnect Reduction............................. T. Kim and X. Liu 641 Accurately Handle Don’t-Care Conditions in High …
RA Thakker, C Sathe, MS Baghini, MB Patil
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